Datasheet

LM97593
www.ti.com SNWS019B –JULY 2007–REVISED APRIL 2013
SCK will be set to the proper strobe rate for each debug tap point. POUT_EN and PSEL[2:0] have no effect in
Debug Mode. The outputs are turned on when the Debug Mode bit is set. Normal serial outputs are also
disabled.
CONTROL REGISTERS
The chip is configured and controlled through the use of 8-bit control registers. These registers are accessed for
reading or writing using the control bus pins (CE, RD, WR, A[7:0], and D[7:0]) described in CONTROL
INTERFACE.
The two sets of FIR coefficients are overlaid at the same memory address. Use the PAGE_SEL registers
to access the second set of coefficients.
The register names and descriptions are listed below in Control Register Addresses and Defaults. A quick
reference table is provided in the Condensed LM97593 Address Map.
Control Register Addresses and Defaults
Register Name Width Type Default
(1)
Addr Bit Description
0(LSBs) 7:0 CIC decimation control. N=DEC+1. Valid range is from 7 to 2047.
DEC 11b R/W 7
1(MSBs) 2:0 Format is an unsigned integer. This affects both channels.
Controls the decimation factor in F2. 0=Decimate by 2.
DEC_BY_4 1b R/W 0 1 4
1=Decimate by 4. This affects both channels.
CIC SCALE parameter. Format is an unsigned integer
representing the number of left bit shifts to perform on the data
SCALE 6b R/W 0 2 5:0
prior to the CIC filter. Valid range is from 0 to 40. This affects
both channels.
GAIN_A 3b R/W 0 3 2:0 Value of left bit shift prior to F1 for channel A.
GAIN_B 3b R/W 0 4 2:0 Value of left bit shift prior to F1 for channel B.
Determines rate of serial output clock. The output rate is
RATE 1B R/W 1 5 7:0 FCK/(RATE+1). Unsigned integer values of 0, 1, 3, 7, 15, and 31
are allowed.
Enables the serial output pins AOUT, BOUT, SCK, and SFS.
SOUT_EN 1b R/W 0 6 0
0=Tristate. 1=Enabled.
Determines polarity of the SCK output. 0=AOUT, BOUT, and
SCK_POL 1b R/W 0 6 1 SFS change on the rising edge of SCK (capture on falling edge).
1=They change on the falling edge of SCK.
Determines polarity of the SFS output. 0=Active High. 1=Active
SFS_POL 1b R/W 0 6 2
Low.
Determines polarity of the RDY output. 0=Active High. 1=Active
RDY_POL 1b R/W 0 6 3
Low.
Determines the mode of the serial outputs. 0=Each channel is
MUX_MODE 1b R/W 0 6 4 output on its respective pin, 1=Both channels are multiplexed and
output on AOUT.
Controls when SFS goes active. 0=SFS pulses prior to the start
of the I and the Q words. 1=SFS pulses only once prior to the
PACKED 1b R/W 0 6 5
start of each I/Q sample pair (i.e. the pair is treated as a double-
sized word) The I word precedes the Q word.
Determines output number format. 0=Truncate serial output to 8
bits. Parallel output is truncated to 32 bits. 1=Round both serial
and parallel to 16-bits. All other bits are set to 0. 2=Round both
FORMAT 2b R/W 0 6 7:6
serial and parallel to 24-bits. All other bits are set to 0. 3=Output
floating point. 8-bit mantissa, 4-bit exponent. All other bits are set
to 0.
Frequency word for channel A. Format is a 32-bit, 2’s
complement number spread across 4 registers. The LSBs are in
FREQ_A 4B R/W 0 7-10 7:0
the lower registers. The NCO frequency F is F/F
CK
=FREQ_A/
2
32
.
(1) These are the default values set by a master reset (MR). Sync in (SI) will not affect any of these values.
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