Datasheet

LM97593
SNWS019B JULY 2007REVISED APRIL 2013
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POWER MANAGEMENT
The LM97593 can be placed in a low power (static) state by stopping the input clock and setting the PD pin high.
To prevent this from placing the LM97593 into unexpected states, the SI pin of the LM97593 should be asserted
prior to disabling the input clock and held asserted until the input clock has returned to a stable condition.
TESTABILITY
JTAG Boundary Scan
The LM97593 supports IEEE 1149.1 compliant JTAG Boundary Scan for the I/O's. The following pins are used:
TRST (test reset)
TMS (test mode select)
TDI (test data in)
TDO (test data out)
TCK (test clock)
The following JTAG instructions are supported:
Instruction Description
BYPASS Connects TDI directly to TDO
EXTEST Enables the test access port controller to drive the outputs
IDCODE Connects the 32-bit ID register to TDO
SAMPLE/PRELOAD Allows the test access port to sample the device inputs and preload
test output data
HIGHZ Tri-states the outputs
The JTAG Boundary Scan can be used to verify printed circuit board continuity at the system level.
Test Register
The user is able to program a value into TEST_REG and substitute this for the normal channel inputs from the
AIN/ BIN pins by selecting it with the crossbar. With the NCO frequency set to zero this allows the DDCs and the
output interface of the chip to be verified. Also, the AGC loop can be opened by setting AGC_HOLD_IC high and
setting the gain of the DVGA by programming the appropriate value into the AGC_IC_A/B register.
Debug Access Port
Real-time access to the following signals is provided by configuring the control interface debug register:
NCO sine and cosine outputs
data after round following mixers
data before F1 and F2
data after CIC filter within the AGC
The access points are multiplexed to a 20-bit parallel output port which is created from signal pins POUT[15:0],
AOUT, BOUT, SFS, and RDY according to the table below:
Normal Mode Pin Debug Mode Pin
POUT[15:0] DEBUG[19:4]
RDY DEBUG[3]
SFS DEBUG[2]
AOUT DEBUG[1]
BOUT DEBUG[0]
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