Datasheet

LM97593

SNWS019B –JULY 2007–REVISED APRIL 2013

www.ti.com

Parallel Port Output Numeric Formats

The I/Q samples can be rounded to 16 or 24 bits or the full 32 bit word can be read. By setting the word size to

32 bits it is possible to read out the top 16-bits and only observe the top 8 bits if desired. Additionally, the output

samples can be formatted as floating point numbers with an 8-bit mantissa and a 4 bit exponent. For the fixed-

point formats, the valid bits are justified into the MSBs of the registers of Table 3 and

Table 3. Register Selection for Parallel Output

POUT_SEL Normal Register Contents Floating Point Register Contents

0 IA upper 16-bits 0000/eIA/mIA

1 IA lower 16-bits 0x0000

2 QA upper 16-bits 0000/eQA/mQA

3 QA lower 16-bits 0x0000

4 IB upper 16-bits 0000/eIB/mIB

5 B lower 16-bits 0x0000

6 QB upper 16-bits 0000/eQB/mQB

7 QB lower 16-bits 0x0000

all other bits are set to zero. For the floating point format, the valid bits are placed in the upper 16-bits of the

appropriate channel register using the format 0000/eI/mI for the I samples.

AGC

The LM97593 AGC processor monitors the output level of the ADC and servos it to the desired setpoint. The

ADC input is controlled by the DVGA to maintain the proper setpoint level. DVGA operation results in a

compression of the signal through the ADC. The DVGA signal compression is reversed in the LM97593 to

provide > 120dB of linear dynamic range. This is illustrated in Figure 77.

Figure 77. Output Gain Scaling vs. Input Signal

In order to use the AGC, the DRCS Control Panel software may be used to calculate the programmable

parameters. To generate these parameters, only the desired setpoint, deadband+ hysteresis, and loop time

constant need to be supplied. All subsequent calculations are performed by the software. Complete details of the

AGC operation are provided in an appendix.

Product Folder Links: LM97593