Datasheet
AOUT
SCK
SFS
RDY
POUT_SEL[0]
SCK_IN
POUT_SEL[1]
POUT_SEL[2]
SDC_EN = 1
MUX_MODE = 0
Master
CLC5903
To DSP
ADCs and
DVGAs
SCK
MASTER
= 2*SCK
SLAVE
AOUT
BOUT
SFS
SCK
SDC_EN = 0
MIX_MODE = 0
PACKED = 1
12
12
4
Slave
CLC5903
12
12
4
ADCs and
DVGAs
LM97593
www.ti.com
SNWS019B –JULY 2007–REVISED APRIL 2013
The serial outputs use the format shown in Figure 75. Figure 75(a) shows the standard output mode (the
PACKED mode bit is low). The chip clocks the frame and data out of the chip on the rising edge of SCK (or
falling edge if the SCK_POL bit in the input control register is set high).
Figure 76. Serial Daisy-Chain Mode
Data should be captured on the falling edge of SCK (rising if SCK_POL=1). The chip sends the I data first by
setting SFS high (or low if SFS_POL in the input control register is set high) for one clock cycle, and then
transmitting the data, MSB first, on as many SCK cycles as are necessary. Without a pause, the Q data is
transferred next as shown in Figure 75(a). If the PACKED control bit is high, then the I and Q components are
sent as a double length word with only one SFS strobe as shown in Figure 75(b). If both channels are
multiplexed out the same serial pin, then the subsequent I/Q channel words will be transmitted immediately
following the first I/Q pair as shown in Figure 75(c). Figure 75(c) also shows how SFS_MODE=1 allows the SFS
signal to be used to identify the A and B channels in the TDM serial transmission. The serial output rate is
programmed by the RATE register to CK divided by 1, 2, 4, 8, 16, or 32. The serial interface will not work
properly if the programmed rate of SCK is insufficient to clock out all the bits in one OSP.
Serial Port Daisy-Chain Mode
Two LM97593s can be connected in series so that a single DSP serial port can receive four DDC output
channels. This mode is enabled by setting the SDC_EN bit to ‘1’ on the serial daisy-chan (SDC) master. The
SDC master is the LM97593 which is connected to the DSP while the SDC slave’s serial output drives the
master. The SDC master’s RATE register must be set so that its SCK rate is twice that of the SDC slave, the
SDC master must have MUX_MODE=1, the SDC slave must have MUX_MODE=0 and PACKED=1, and both
chips must come out of a MR or SI event within four CK periods of each other. In this configuration, the master’s
serial output data is shifted out to the DSP and then the slave’s serial data is shifted out. All the serial output data
will be muxed onto the master’s AOUT pin as shown in Figure 76.
Serial Port Output Number Formats
Several numeric formats are selectable using the FORMAT control register. The I/Q samples can be rounded to
16 or 24 bits, or truncated to 8 bits. The packed mode works as described above for these fixed point formats. A
floating point format with 138dB of dynamic range in 12 bits is also provided. The mantissa (m) is 8 bits and the
exponent (e) is 4 bits. The MSB of each segment is transmitted first. When the packed mode is selected, the I/Q
samples are packed regardless of the state of MUX_MODE, and the data is sent as mI/eI/eQ/ mQ which allows
the two exponents to form an 8-bit word. This is shown in Figure 75(d). For all formats, once the defined length
of the word is complete, SCK stops toggling.
Parallel Outputs
Output data from the channels can also be taken from a 16-bit parallel port. A 3-bit word applied to the
POUT_SEL[2:0] pins determines which 16-bit segment is multiplexed to the parallel port. Table 3 defines this
mapping. To allow for bussing of multiple chips, the parallel port is tri-stated unless POUT_EN is low. The RDY
signal indicates the start of an OSP and that new data is ready at the parallel output. The user has one OSP to
cycle through whichever registers are needed. The RATE register must be set so that each OSP is at least 5
SCK periods.
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