Datasheet
LM97593
SNWS019B –JULY 2007–REVISED APRIL 2013
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Refer to Figure 13 for detailed timing information.
Figure 75. Serial output formats
Serial Outputs
The LM97593 provides a serial clock (SCK), a frame strobe (SFS) and two data lines (AOUT and BOUT) to
output serial data. The MUX_MODE control register specifies whether the two channel outputs are transmitted
on two separate serial pins, or multiplexed onto one pin in a time division multiplexed (TDM) format. Separate
output pins are not provided for the I and Q halves of complex data. The I and Q outputs are always multiplexed
onto the same serial pin. The I-component is output first, followed by the Q-component. By setting the PACKED
mode bit to ‘1’ a complex pair may be treated as a single double-wide word. The RDY signal is used to identify
the first word of a complex pair of the TDM formatted output when the SFS_MODE bit is set to ‘0’. Setting
SFS_MODE to ‘1’ causes the LM97593 to output a single SFS pulse for each output period. This SFS pulse will
be coincident with RDY and only a single SCK period wide. The TDM modes are summarized in Table 2.
Table 2. TDM Modes
SERIAL OUTPUTS
SFS_MODE MUX_MODE
AOUT BOUT
0 0 OUT
A
OUT
B
1 OUT
A
, OUT
B
LOW
1 0 OUT
A
OUT
B
1 OUT
A
, OUT
B
LOW
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