Datasheet

LM97593
SNWS019B –JULY 2007–REVISED APRIL 2013 www.ti.com
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin No. Symbol Equivalent Circuit Description
SERIAL DATA CLOCK, Active high or low
The serial data is clocked out of the chip by this clock. The active edge of
the clock is user programmable. This pin is tri-stated at power up and is
80 SCK Output enabled by the SOUT_EN control register bit. See Figure 13 and
Figure 75 timing diagrams. In Debug Mode outputs an appropiate clock
for the debug data. If RATE=0 the input CK duty cycle will be reflected to
SCK.
SERIAL DATA CLOCK INPUT, Active high or low
Data bits from a serial daisy-chain slave are clocked into a serial daisy-
99 SCK_IN Input
chain master on the falling edge of SCK_IN (rising if SCK_POL=1 on the
slave). Tie low if not used.
SERIAL FRAME STROBE, Active high or low
The serial word strobe. This strobe delineates the words within the serial
output streams. This strobe is a pulse at the beginning of each serial
81 SFS Output word (PACKED=0) or each serial word I/Q pair (PACKED=1). The polarity
of this signal is user programmable. This pin is tri-stated at power up and
is enabled by the SOUT_EN control register bit. See Figure 13 and
Figure 75 timing diagrams. In Debug Mode SFS=DEBUG[2].
84, 86:88, PARALLEL OUTPUT DATA, Active high
90, 91, The output data is transmitted on these pins in parallel format. The
93:97, POUT[15:0] Output POUT_SEL[2:0] pins select one of eight 16-bit output words. The
104:106, POUT_EN pin enables these outputs. POUT[15] is the MSB. In Debug
108, 109 Mode POUT[15:0]=DEBUG[19:4].
PARALLEL OUTPUT DATA SELECT, Active high
The 16-bit output word is selected with these 3 pins. Not used in Debug
112:114 POUT_SEL[2:0] Input Mode. For a serial daisy-chain master, POUT_SEL[2:0] become inputs
from the slave: POUT_SEL[2]=SFS
SLAVE
, POUT_SEL[1]=BOUT
SLAVE
,
and POUT_SEL[0]=AOUT
SLAVE
. Tie low if not used.
PARALLEL OUTPUT ENABLE. Active low
111 POUT_EN Input This pin enables the chip to output the selected output word on the
POUT[15:0] pins. Not used in Debug Mode. Tie high if not used.
READY FLAG, Active high or low
The chip asserts this signal to identify the beginning of an output sample
period (OSP). The polarity of this signal is user programmable. This
77 RDY Output
signal is typically used as an interrupt to a DSP chip, but can also be
used as a start pulse to dedicated circuitry. This pin is active regardless
of the state of SOUT_EN. In Debug Mode RDY=DEBUG[3].
INPUT CLOCK. Active high
The clock input to the chip. The The V
IN
A and V
IN
B analog input signals
37 CK Input
are sampled on the rising edge of this signal. SI is clocked into the chip
on the rising edge of CK.
SYNC IN. Active low
The sync input to the chip. The decimation counters, dither, and NCO
phase can be synchronized by SI. This sync is clocked into the chip on
46 SI Input
the rising edge of CK. Tie this pin high if external sync is not required. All
sample data is flushed by SI. To properly initialize the DVGA ASTROBE
and BSTROBE are asserted during SI.
DATA BUS. Active high
62, 63, This is the 8 bit control data I/O bus. Control register data is loaded into
D[7:0] Input/Output
69:73, 75 the chip or read from the chip through these pins. The chip will only drive
output data on these pins when CE is low, RD is low, and WR is high.
ADDRESS BUS. Active high
These pins are used to address the control registers within the chip. Each
48, 50, 52:57 A[7:0] Input of the control registers within the chip are assigned a unique address. A
control register can be written to or read from by setting A[7:0] to the
register’s address and setting CE, RD, and WR appropriately.
READ ENABLE. Active low
59 RD Input This pin enables the chip to output the contents of the selected register
on the D[7:0] pins when CE is also low.
WRITE ENABLE. Active low
This pin enables the chip to write the value on the D[7:0] pins into the
58 WR Input
selected register when CE is also low. This pin can also function as RD/
CE if RD is held low. See Figure 15 for details.
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