Datasheet

LM97593

SNWS019B –JULY 2007–REVISED APRIL 2013

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Overall Channel Gain

The overall gain of the chip is a function of the amount of decimation (N), the settings of the “SHIFT UP” circuit

(SCALE), the GAIN setting, the sum of the F1 coefficients, and the sum of the F2 coefficients. The overall gain is

shown below in Equation 6.

(6)

Where:

(7)

and:

(8)

It is assumed that the DDC output words are treated as fractional 2’s complement words. The numerators of G

and G

equal the sums of the impulse response coefficients of F1 and F2, respectively. For the STD and GSM

sets, G

and G

are nearly equal to unity. Observe that the AGAIN term in Equation 6 is cancelled by the

DVGA operation so that the entire gain of the DRCS is independent of the DVGA setting when EXP_INH=0. The

1/2 appearing in Equation 6 is the result of the 6dB conversion loss in the mixer. For full-scale square wave

inputs the 1/2 should be set to 1 to prevent signal distortion.

Data Latency and Group Delay

The LM97593 latency calculation assumes that the FIR filter latency will be equal to the time required for data to

propagate through one half of the taps. The CIC filter provides 4N equivalent taps where N is the CIC decimation

ratio. F1 and F2 provide 21 and 63 taps respectively. When these filters are reflected back to the input rate, the

effective taps are increased by decimation. This results in a total of 151N taps.

The total latency is found by dividing the number of taps by 2 and adding pipeline delays. When the F2

decimation is 2 the latency is 80N. When the F2 decimation is 4 the latency is 82N. The LM97593 filters are

linear phase filters so the group delay remains constant.

OUTPUT MODES

After processing by the DDC, the data is then formatted for output.

All output data is two’s complement. The serial outputs power up in a tri-state condition and must be

enabled when the chip is configured. Parallel outputs are enabled by the POUT_EN pin.

Output formats include truncation to 8 or 32 bits, rounding to 16 or 24 bits, and a 12-bit floating point format (4-bit

exponent, 8-bit mantissa, 138dB numeric range). This function is performed in the OUTPUT CIRCUIT shown in

Figure 74.

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