Datasheet

LM97593

SNWS019B –JULY 2007–REVISED APRIL 2013

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The 16 bit phase offset is set by loading the PHASE register according to the formula PHASE = 2

P/2π, where

P is the desired phase in radians ranging between 0 and 2π. PHASE is an unsigned 16-bit number. P ranges

from 0 to 2π(1-2

-16

). Phase dithering can be enabled to reduce the spurious signals created by the NCO due to

phase truncation. This truncation is unavoidable since the frequency resolution is much finer than the phase

resolution. With dither enabled, spurs due to phase truncation are below -100 dBc for all frequencies and phase

offsets. Each NCO has its own dither source and the initial state of one is maximally offset with respect to the

other so that they are effectively uncorrelated. The phase dither sources are on by default. They are

independently controlled by the DITH_A and DITH_B bits. The amplitude resolution of the ROM creates a worst-

case spur amplitude of -101dBc rendering amplitude dither unnecessary.

The spectrum plots in Figure 61 and Figure 62show the effectiveness of phase dither in reducing NCO spurs due

to phase truncation for a worst-case example (just below F

/8). With dither off, the spur is at -86.4dBFS. With

dither on, the spur is below -125dBFS, disappearing into the noise floor. This spur is spread into the noise floor

which results in an SNR of -83.6dBFS. The channel filter’s processing gain will further improve the SNR.

Figure 63 shows the spur levels as the tuning frequency is scanned over a narrow portion of the frequency

range. The spurs are again a result of phase quantization but their locations move about as the frequency scan

progresses. As before, the peak spur level drops when dithering is enabled. When dither is enabled and the

fundamental frequency is exactly at F

/8, the worst-case spur due to amplitude quantization can be observed at -

101dBc in Figure 64.

Four Stage CIC Filter

The mixer outputs are decimated by a factor of N in a four stage CIC filter. N is programmable to any integer

between 8 and 2048. Decimation is programmed in the DEC register where DEC = N - 1. The programmable

decimation allows the chip’s usable output bandwidth to range from about ±1.27kHz to ±650kHz when the input

data rate (which is equal to the chip’s clock rate, F

) is 52 MHz. For the maximum sample rate of 65MHz, the

LM97593’s output bandwidth will range from about ±1.58kHz to ±812kHz. A block diagram of the CIC filter is

shown in Figure 65.

The CIC filter is primarily used to decimate the high-rate incoming data while providing a rough lowpass

characteristic. The lowpass filter will have a sin(x)/x response (similar to the AGC’s CIC shown in Figure 80)

where the first null is at F

/N.

Figure 63. Complex NCO Output Phase Dither Disabled

NCO Spurs due to Phase Quantization

Product Folder Links: LM97593