Datasheet
SHIFT UP
SHIFT UP
CIC FILTER
DECIMATION BY
8 TO 2k
SAT & ROUND
SAT & ROUND
SAT
TO
OUTPUT
CIRCUIT
ROUND
FLOAT
TO FIXED
CONVERTER
N = DEC + 1
Data @ F
CK
/N
SCALE
DEC
GAIN_A
F1_COEF
F2_COEF
DEC_BY_4
Data @ F
CK
/N*2
Data @ F
CK
/N*2*F2_DEC
= O
FS
(Output F
SAMPLE
)
Data @ F
CK
= F
S
(F
SAMPLE
)
PHASE_A
FREQ_A
MUXA
EXP
(from AGC)
EXP_INH
EXP
NCO
F2 FILTER
DECIMATE BY
2 OR 4
F1 FILTER
DECIMATE BY 2
COSSIN
17 17
15
22
21
21
15
3
14
22
21
21
EXPONENT
Q
I
LM97593
SNWS019B –JULY 2007–REVISED APRIL 2013
www.ti.com
The “FLOAT TO FIXED CONVERTER” circuit expands the dynamic range compression performed by the DVGA.
Signals from this point onward extend across the full dynamic range of the signals applied to the DVGA input.
This allows the AGC to operate continuously through a burst without producing artifacts in the signal due to the
settling response of the decimation filters after a 6dB DVGA gain adjustment. For example, if the DVGA input
signal were to increase causing the ADC output level to cross the AGC threshold level, the gain of the DVGA
would change by -6dB. The 6dB step is allowed to propagate through the ADC and mixers and is compensated
out just before the filtering. The accuracy of the compensation is dependent on timing and the accuracy of the
DVGA gain step. The LM97593 allows the timing of the gain compensation to be adjusted in the EXT_DELAY
register; see the end of section AGC for more information. The AGC requires 21 bits (14-bit internal bus output +
7-bit shift) to represent the full linear dynamic range of the signal. The output word must be set to either 24-bit or
32-bit to take advantage of the entire dynamic range available. The LM97593 can also be configured to output a
floating point format with up to 138dB of numerical resolution using only 12 output bits.
Figure 60. LM97593 Down Converter, Channel A (Channel B is identical)
The “SHIFT UP” circuit will be discussed in the section Four Stage CIC Filter.
A 4-stage cascaded-integrator-comb (CIC) filter and a two-stage decimate by 4 or 8 finite impulse response (FIR)
filter are used to lowpass filter and isolate the desired signal. The CIC filter reduces the sample rate by a
programmable factor ranging from 8 to 2048 (decimation ratio). The CIC outputs are followed by a gain stage
and then followed by a two-stage decimate by 4 or 8 filter. The gain circuit allows the user to boost the gain of
weak signals by up to 42 dB in 6 dB steps. It also rounds the signal to 21 bits and saturates at plus or minus full
scale.
The first stage of the two stage filter is a 21-tap, symmetric decimate by 2 FIR filter (F1) with programmable 16
bit tap weights. The coefficients of the first 11 taps are downloaded to the chip as 16 bit words. Since the filter is
a symmetric configuration only the first 11 coefficients must be loaded. First Programmable FIR Filter (F1)
provides a generic set of coefficients that compensate for the rolloff of the CIC filter and provide a passband flat
to 0.01dB with 70 dB of out of band rejection. A second coefficient set is provided that has a narrower output
passband and greater out-of-band rejection. The second set of coefficients is ideal for systems such as GSM
where far-image rejection is more important than adjacent channel rejection.
The second stage is a 63 tap decimate by 2 or 4 programmable FIR filter (F2) also with 16 bit tap weights. Filter
coefficients for a flat response from -0.4FS to +0.4FS of the output sample rate with 80dB of out of band rejection
are provided in Second Programmable FIR Filter (F2). A second set of F2 coefficients is also provided to
enhance performance for GSM systems. The user can also design and download their own final filter to
customize the channel’s spectral response. Typical uses of programmable filter F2 include matched (root-raised
cosine) filtering, or filtering to generate oversampled outputs with greater out of band rejection. The 63 tap
symmetrical filter is downloaded into the chip as 32 words, 16 bits each. Saturation to plus or minus full scale is
performed at the output of F1 and F2 to clip the signal rather than allow it to roll over.
30 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LM97593