Datasheet

ADC_A
ADC_B
MUX
MUX
AOUT/BOUT
BOUT
SCK
SFS
RDY
POUT[15:0]
PSEL[2:0]
POUT_EN
ASTROBE
BGAIN[2:0]
BSTROBE
14
14
A
B
Channel A
SCK_IN
TEST_REG
Channel B
12
12
Output
Formatter
AGAIN[2:0]
Tuning,
Channel Filters, and
AGC
Tuning,
Channel Filters, and
AGC
V
IN
A
V
IN
B
LM97593
www.ti.com SNWS019B –JULY 2007–REVISED APRIL 2013
Block Diagram 2
Figure 3. LM97593 Block Diagram
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
13 V
IN
A− Negative differential input signal for the 'A' channel
Analog Input
27 V
IN
B− Negative differential input signal for the 'B' channel
14 V
IN
A+ Positive differential input signal for the 'A' channel
Analog Input
26 V
IN
B+ Positive differential input signal for the 'B' channel
Reference Select Pin / External Reference Voltage Input
Input differential full scale swing = 2 * V
REF
21 V
REF
Control / Analog Input
V
REF
= V
A
to V
A
- 0.3V: Reference Voltage = 1.0 V (Internal)
V
REF
= 0.8V to 1.5V: Reference Voltage = V
REF
(External)
Common Mode reference voltage for the 'A' channel
15 V
COM
A Common Mode reference voltage for the 'B' channel
Analog Output
24 V
COM
B These pins may be loaded to 1 mA for use as temperature stable 1.5V
references.
16 V
RP
A Upper reference voltage for the 'A' channel
Analog Output
23 V
RP
B Upper reference voltage for the 'B' channel
17 V
RN
A Lower reference voltage for the 'A' channel
Analog Output
22 V
RN
B Lower reference voltage for the 'B' channel
This is a three-state pin. V
COM
= V
COM
A or V
COM
B.
REFSEL/DCS = AGND: the internal reference is enabled and duty cycle
correction is applied to the ADC input clock (CK).
8 REFSEL/DCS Control Input REFSEL/DCS = V
COM
: the internal reference is enabled and no duty
cycle correction is applied to the ADC input clock (CK).
REFSEL/DCS = V
A
: DCS is on, the internal reference is disabled. Apply
A 0.8-1.2V external reference to the V
REF
pin.
DIGITAL I/O
POWER DOWN, when high both ADCs are powered down, when low,
30 PD Input
both ADCs are enabled
MASTER RESET, Active low
45 MR Input Resets all registers within the chip. ASTROBE and BSTROBE are
asserted during MR.
SERIAL OUTPUT DATA, Active high
The 2's complement serial output data is transmitted on these pins, MSB
first. The output bits change on the rising edge of SCK (falling edge if
82 AOUT
Output SCK_POL=1) and should be captured on the falling edge of SCK (rising if
78 BOUT
SCK_POL=1). These pins are tri-stated at power up and are enabled by
the SOUT_EN control register bit. See Figure 13 and Figure 75 timing
diagrams. In Debug Mode AOUT=DEBUG[1], BOUT=DEBUG[0].
127:125 AGAIN[2:0] OUTPUT DATA TO DVGA, Active high
Output
40:42 BGAIN[2:0] 3 bit bus that sets the gain of the DVGA determined by the AGC circuit.
DVGA STROBE, Active low
124 ASTROBE
Output Strobes the data into the DVGA. See Figure 7 and Figure 82 timing
43 BSTROBE
diagrams.
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