Datasheet

LM97593
www.ti.com SNWS019B –JULY 2007–REVISED APRIL 2013
DDC Application Information
CONTROL INTERFACE
The LM97593 is configured by writing control information into 237 control registers within the chip. The contents
of these control registers and how to use them are described in Control Register Addresses and Defaults. The
registers are written to or read from using the D[7:0], A[7:0], CE, RD and WR pins. This interface is designed to
allow the LM97593 to appear to an external processor as a memory mapped peripheral. See Figure 15 for
details.
The control interface is asynchronous with respect to the system clock, CK. This allows the registers to be
written or read at any time. In some cases this might cause an invalid operation since the interface is not
internally synchronized. In order to assure correct operation, SI must be asserted after the control registers are
written.
The D[7:0], A[7:0], WR, RD and CE pins should not be driven above the positive supply voltage.
Master Reset
A master reset pin, MR, is provided to initialize the LM97593 to a known condition and should be strobed after
power up. This signal will clear all sample data and all user programmed data (filter coefficients and AGC
settings). All outputs will be disabled (tri-stated). ASTROBE and BSTROBE will be asserted to initialize the
DVGA values. Control Register Addresses and Defaults describes the control register default values.
Synchronizing Multiple LM97593 Chips
A system containing two or more LM97593 chips will need to be synchronized if coherent operation is desired.
To synchronize multiple LM97593 chips, connect all of the sync input pins together so they can be driven by a
common sync strobe. Synchronization occurs on the first rising edge of CK after SI goes high. When SI is
asserted all sample data is immediately cleared, the numerically controlled oscillator (NCO) phase offset is
initialized, the NCO dither generators are reset, and the CIC decimation ratio is initialized. Only the configuration
data loaded into the microprocessor interface remains unaffected.
SI may be held low as long as desired after a minimum of 4 CK periods.
Input Source
The input crossbar switch allows either V
IN
A, V
IN
B, or a test register to be routed to the channel A or channel B
AGC/ DDC. The AGC outputs, AGAIN and BGAIN, are not switched. If V
IN
A and V
IN
B are exchanged the AGC
loop will be open and the AGC will not function properly.
Selecting the test register as the input source allows the AGC or DDC operation to be verified with a known
input. See Test Register for further discussion.
DOWN CONVERTERS
A detailed block diagram of each DDC channel is shown in Figure 60. Each down converter uses a complex
NCO and mixer to quadrature downconvert a signal to baseband. The “FLOAT TO FIXED CONVERTER” treats
the 15-bit mixer output as a mantissa and the AGC output, EXP, as a 3-bit exponent. It performs a bit shift on the
data based on the value of EXP. This bit shifting is used to expand the compressed dynamic range resulting from
the DVGA operation. The DVGA gain is adjusted in 6dB steps which are equivalent to each digital bit shift.
Digitally compensating for the DVGA gain steps in the LM97593 causes the DDC output to be linear with respect
to the DVGA input. The AGC operation will be completely transparent at the LM97593 output.
The exponent (EXP) can be forced to its maximum value by setting the EXP_INH bit. If x
in
(n) is the DDC input,
the signal after the “FLOAT TO FIXED CONVERTER” is
x
3
(n) = x
in
(n)*cos(ωn)*2
EXP
(5)
for the I component. Changing the ‘cos’ to ‘sin’ in this equation will provide the Q component.
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