Datasheet

LM97593
SNWS019B –JULY 2007–REVISED APRIL 2013 www.ti.com
The clock line should be terminated at its source in the characteristic impedance of that line. Take care to
maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905
(literature number SNLA035) for information on setting characteristic impedance.
It is highly desirable that the the source driving the ADC CLK pin only drive that pin. However, if that source is
used to drive other things, each driven pin should be a.c. terminated with a series RC to ground such that the
resistor value is equal to the characteristic impedance of the clock line and the capacitor value is
where
• t
PD
is the signal propagation time down the clock line
• "L" is the line length
• Z
O
is the characteristic impedance of the clock line (4)
This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock
source. Typical t
PD
is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and t
PD
should be
the same (inches or centimeters).
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise
duty cycle is difficult, the LM97593 has a Duty Cycle Stabilizer which can be enabled using the REFSEL/DCS
pin. It is designed to maintain performance over a clock duty cycle range of 30% to 70% at 65 MSPS.
REFSEL/DCS
This pin is used in conjunction with V
REF
(pin 21) to select the reference source and turn the Duty Cycle
Stabilizer (DCS) on or off.
When REFSEL/DCS is LOW and V
REF
is HIGH, the internal 1.0V reference is selected and DCS is On.
When REFSEL/DCS is HIGH, an external reference voltage in the range of 0.8V to 1.2V should be applied to the
VREF input. DCS is On.
With REFSEL/DCS pin connected to V
COM
A or V
COM
B, the internal 1.0V reference is selected and DCS is Off.
When enabled, duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to
70% and generate a stable internal clock, improving the performance of the part.
Table 1. V
REF
, REFSEL/DCS Pin Functions
REFSEL/DCS (pin 8) V
REF
(pin 21) Reference DCS
Logic Low Logic High Internal 1.0 V ON
Logic High 0.8 to 1.2V External ON
V
COM
A or V
COM
B Logic High Internal 1.0V OFF
V
COM
A or V
COM
B 0.8 to 1.2V External OFF
PD
The PD pin, when high, holds the ADC in a power-down mode to conserve power when the converter is not
being used. The output data pins are undefined and the data in the pipeline is corrupted while in the power down
mode.
The Power Down Mode Exit Cycle time is determined by the value of the components on pins 15, 16, 17, 22, 23
and 24. These capacitors lose their charge in the Power Down mode and must be recharged by on-chip circuitry
before conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down
mode, but can result in a reduction in SNR, SINAD and ENOB performance.
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