Datasheet

LM97593
www.ti.com SNWS019B –JULY 2007–REVISED APRIL 2013
Figure 59. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause
Distortion
For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage equal
to the reference voltage, V
REF
, be 180 degrees out of phase with each other and be centered around V
CM
.
Single-Ended Operation
Performance with differential input signals is better than with single-ended signals. For this reason, single-ended
operation is not recommended. However, if single ended-operation is required and the resulting performance
degradation is acceptable, one of the analog inputs should be connected to the d.c. mid point voltage of the
driven input. The peak-to-peak input signal at the driven input pin should be twice the reference voltage to
maximize SNR and SINAD performance (Figure 58b). For example, set V
REF
to 1.0V, bias V
IN
− to 1.5V and drive
V
IN
+ with a signal range of 0.5V to 2.5V.
Because very large input signal swings can degrade distortion performance, better performance with a single-
ended input can be obtained by reducing the reference voltage when maintaining a full-range output.
Driving the Analog Inputs
The V
IN
+ and the V
IN
− inputs of the ADC consist of an analog switch followed by a switched-capacitor amplifier.
As the internal sampling switch opens and closes, current pulses occur at the analog input pins, resulting in
voltage spikes at the signal input pins. As the driving source attempts to counteract these voltage spikes, it may
add noise to the signal at the ADC analog input. C1, C2, and C3 as shown in Figure 86 improve the ADC
performance by filtering these voltage spikes. These components should be placed close to the ADC inputs
because the input pins of the ADC are the most sensitive part of the system and this is the last opportunity to
filter that input.
For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the
sample mode should be considered when setting the RC pole. For wideband undersampling applications, the RC
pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear delay response. The
values of the RC shown in Figure 86 are suitable for applications with input frequencies up to approximately
70MHz.
Input Common Mode Voltage
The input common mode voltage, V
CM
, should be in the range of 1.0V to 2.0V and be a value such that the peak
excursions of the analog signal do not go more negative than ground or more positive than 2.6V. See Reference
Pins.
DIGITAL INPUTS
Digital TTL/CMOS compatible inputs consist of CK, REFSEL/DCS.
CLK
The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock
signal in the range of 10 MHz to 65 MHz. The higher the input frequency, the more critical it is to have a low jitter
clock. The trace carrying the clock signal should be as short as possible and should not cross any other signal
line, analog or digital, not even at 90°.
The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency too low, the
charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This
is what limits the lowest sample rate.
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