Datasheet

LM97593
www.ti.com SNWS019B –JULY 2007–REVISED APRIL 2013
The frequencies, phase offsets, and phase dither of the two sine/cosine numerically controlled oscillators (NCOs)
can be independently specified. Two sets of coefficient memories and a crossbar switch allow shared or
independent filter coefficients and bandwidth for each channel. Both channels share the same decimation ratio
and input/output formats.
Each channel has its own AGC circuit for use with narrowband radio channels where most of the channel filtering
precedes the ADC. The AGC closes the loop around the DVGA, compressing the dynamic range of the signal
into the ADC. AGC gain compensation in the LM97593 removes the DVGA gain steps at the output. The time
alignment of this gain compensation circuit can be adjusted. The AGC can be configured to operate continuously
or set to a fixed gain. The two AGC circuits operate independently but share the same programmed parameters
and control signals.
The chip receives configuration and control information over a microprocessor-compatible bus consisting of an 8-
bit data I/O port, an 8-bit address port, a chip enable strobe, a read strobe, and a write strobe. The chip’s control
registers (8 bits each) are memory mapped into the 8-bit address space of the control port. Page select bits allow
access to the overlaid A and B set of FIR coefficients.
JTAG boundary scan and on-chip diagnostic circuits are provided to simplify system debug and test.
The LM97593 supports 3.3V I/O even though the core logic voltage is 1.8V. The LM97593 outputs swing to the
3.3V rail so they can be directly connected to 5V TTL inputs if desired.
ADC Application Information
ADC OPERATING CONDITIONS
We recommend that the following conditions be observed for operation:
3.0V ≤ V
A
≤ 3.6V
V
D
= V
A
= V
DR
V
D18
= 1.8V
10 MHz ≤ f
CLK
≤ 65 MHz
1.0 V internal reference
V
CM
= 1.5V (from V
COM
A and V
COM
B)
Analog Inputs
There is one reference input pin, V
REF
, which is used to select an internal reference, or to supply an external
reference. The ADC has two analog signal input pairs, V
IN
A+ and V
IN
A- for one converter and V
IN
B+ and V
IN
B-
for the other converter. Each pair of pins forms a differential input pair.
Reference Pins
The ADC is designed to operate with an internal 1.0V reference or an external 1.0V reference, but performs well
with external reference voltages in the range of 0.8V to 1.2V. Lower reference voltages will decrease the signal-
to-noise ratio (SNR) of the ADC. Increasing the reference voltage (and the input signal swing) beyond 1.2V may
degrade THD for a full-scale input, especially at higher input frequencies.
It is important that all grounds associated with the reference voltage and the analog input signal make connection
to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.
The six Reference Bypass Pins (V
RP
A, V
COM
A, V
RN
A, V
RP
B, V
COM
B and V
RN
B) are made available for bypass
purposes. All these pins should each be bypassed to ground with a 0.1 µF capacitor. A 10 µF capacitor should
be placed between the V
RP
A and V
RN
A pins and between the V
RP
B and V
RN
B pins, as shown in Figure 86. This
configuration is necessary to avoid reference oscillation, which could result in reduced SFDR and/or SNR.
Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may
result in degraded noise performance. Loading any of these pins other than V
COM
A and V
COM
B may result in
performance degradation.
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