Datasheet

LM97593

SNWS019B –JULY 2007–REVISED APRIL 2013

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FUNCTIONAL DESCRIPTION

Figure 57. LM97593 Dual ADC / Digital Tuner / AGC Block Diagram with Control Register Associations

The LM97593 contains two identical 12-bit ADCs driving the digital down-conversion (DDC) circuitry shown in the

block diagram in Figure 57.

ADC

The ADCs operate off of a +3.3V supply and use a pipeline architecture with error correction circuitry to help

ensure maximum performance. The differential analog input signal is digitized to 12 bits. The user has the choice

of using an internal 1.0 Volt or an external reference. Any external reference is buffered on-chip to ease the task

of driving that pin.

The clock frequency is rated up to 65 MHz. The analog input for both channels is acquired at the rising edge of

the clock. The digital data for a given sample is delayed by the pipeline for 7 clock cycles before it reaches the

input to the DDC circuit. A logic high on the power down (PD) pin reduces the converter power consumption to

50 mW. The DDC power can be further reduced by gating off the clock as described in section POWER

MANAGEMENT.

DDC

Each independent DDC channel down converts the sub-sampled IF to baseband, decimates the signal rate by a

programmable factor ranging from 32 to 16384, provides channel filtering, and outputs quadrature symbols.

A crossbar switch enables either of the two inputs or a test register to be routed to either DDC channel. Flexible

channel filtering is provided by the two programmable decimating FIR filters. The final filter outputs can be

converted to a 12-bit floating point format or standard two’s complement format. The output data is available at

both serial and parallel ports.

The LM97593’s DDC maintains over 100 dB of spurious free dynamic range and over 100 dB of out-of-band

rejection. This allows considerable latitude in channel filter partitioning between the analog and digital domains.

Product Folder Links: LM97593