Datasheet

BGAIN[2]
A[5]
V
DR
D18GND
BGAIN[0]
BGAIN[1]
~BSTROBE
D18GND
~MR
~SI
DRGND
A[7]
V
D18
A[4]
A[3]
A[2]
A[1]
A[0]
~WR
~RD
~CE
D[7]
D[6]
V
DR
A[6]
AGAIN[2]
V
D18
V
DR
TDO
AGAIN[0]
AGAIN[1]
~ASTROBE
V
D18
~SCAN_EN
~TRST
D18GND
TCK
TMS
POUT_SEL[0]
POUT_SEL[1]
POUT_SEL[2]
~POUT_EN
DRGND
POUT[0]
POUT[1]
V
DR
POUT[3]
POUT[2]
POUT[4]
D18GND
TDI
CK V
A
V
DR
V
IN
B+
NC NC V
D
DGND DGND V
D
PD V
A
AGND V
COM
B
V
RP
B
V
RN
B
V
REF
AGND V
A
AGND V
RN
A
V
COM
A
V
RP
A
V
IN
A+
V
IN
A-
V
IN
B-
V
A
AGND AGND V
A
REFSEL/DCS DGND V
D
DGND V
D
NC AGND DRGND
LM97593VH
Dual Digital Tuner / AGC / ADC
(Top View)
D18GND
BOUT
D18GND
RDY
DRGND
NC
D[5] D[4] D[3] D[2] D[1]
V
D18
D[0]
V
DR
SCK
SFS
AOUT
DRGND
POUT[15]
V
D18
POUT[14] POUT[12] POUT[13]
DRGND
POUT[11]
D18GND
V
DR
POUT[10]
POUT[8] POUT[9] POUT[7] POUT[6] POUT[5]
DRGND
SCK_IN
NC NC
V
DR
DRGND
40
52
39
51
42
41
43
44
45
46
47
48
49
53
54
55
56
57
58
59
60
62
61
63
64
50
127
115
128
116
125
126
124
123
122
121
120
119
118
114
113
112
111
110
109
108
107
105
106
104
103
117
66 78 65 77 68 67 69 70 71 72 73 74 75 79 80 81 82 83 84 85 86 88 87 89 90 76 92 91 94 93 95 96 97 98 99
100 101 102
37 25 38 26 35 36 34 33 32 31 30 29 28 24 23 22 21 20 19 18 17 15 16 14 13 27 11 12
9
10
8 7 6 5 4 3 2 1
DVGA
IF A
SerialOutA/B
SerialOutB
SCK
SFS
RDY
LC
DVGA
IF B
LC
ParallelOutput[15:0]
ParallelOutputEnable
ParallelSelect[2:0]
CLC5526
CLK
12
8
12
ADC
SCK_IN
Dual Digital
Tuner/AGC
LM97593
(x2)
ADC
LM97593
SNWS019B –JULY 2007–REVISED APRIL 2013 www.ti.com
Block Diagram 1
Figure 1. Diversity Receiver Chipset Block Diagram
Connection Diagram
Figure 2. LM97593VH PQFP Pinout
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