Datasheet

A|BSTROBE
A|BGAIN[2:0]
t
GSTB
t
STIW
CK
t
RF
V
IL
V
IH
t
CKDC
t
CKDC
1
F
CK
CK
t
SISU
t
SIH
SI
t
SIW
t
MRA
t
MRH
t
MRSU
t
MRIC
CK
MR
RD
or WR
LM97593
www.ti.com SNWS019B –JULY 2007–REVISED APRIL 2013
AC Electrical Characteristics (continued)
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = D18GND = 0V, V
A
= V
D
= V
DR
=
+3.3V (±10%), V
D18
= +1.8V (±10%), Internal V
REF
= +1.0V, f
CLK
= 65 MHz, V
CM
= V
COM
, t
R
= t
F
= 1 ns, C
L
= 5 pF/pin. CIC
Decimation = 48, F2 Decimation = 2. Typical values are for T
A
= 25°C. Boldface limits apply for T
MIN
≤ T
A
≤ T
MAX
. All other
limits apply for T
A
= 25°C.
(1)
Typical
Symbol Parameter (C
L
=50pF) Min Max Units
(2)
t
JCH
TCK Pulse Width High (Figure 14) 50 ns
t
JCL
TCK Pulse Width Low (Figure 14) 40 ns
JTAG
FMAX
TCK Maximum Frequency (Figure 14) 10 MHz
Microprocessor Interface
t
CSU
Control Setup before the controlling signal goes low (Figure 15) 5 ns
t
CHD
Control hold after the controlling signal goes high (Figure 15) 5 ns
t
CSPW
Controlling strobe pulse width (Write) (Figure 15) 30 ns
t
CDLY
Control output delay controlling signal low to D (Read) (Figure 15) 30 ns
t
CZ
Control tri-state delay after controlling signal high (Figure 15) 20 ns
DDC Timing Diagrams
Figure 4. LM97593 Master Reset Timing
Figure 5. LM97593 Synchronization Input (SI) Timing
Figure 6. LM97593 Clock Timing
Figure 7. LM97593 DVGA Interface Timing
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LM97593