Datasheet

LM97593
SNWS019B –JULY 2007–REVISED APRIL 2013 www.ti.com
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = D18GND = 0V, V
A
= V
D
= V
DR
=
+3.3V (±10%), V
D18
= +1.8V (±10%), Internal V
REF
= +1.0V, f
CLK
= 65 MHz, V
CM
= V
COM
, t
R
= t
F
= 1 ns, C
L
= 5 pF/pin. CIC
Decimation = 48, F2 Decimation = 2. Typical values are for T
A
= 25°C. Boldface limits apply for T
MIN
≤ T
A
≤ T
MAX
. All other
limits apply for T
A
= 25°C.
(1)
Typical
Symbol Parameter (C
L
=50pF) Min Max Units
(2)
Clock Input
F
CK
Clock (CK) Frequency (Figure 6) 20 65 MHz
t
CKDC
CK duty cycle, DCS off (Figure 6) 40 60 %
t
RF
CK rise and fall times (V
IL
to V
IH
) (Figure 6) 2 ns
NCO Tuning Resolution 0.02 Hz
NCO Phase Resolution 0.005 o
Control Interface
t
MRA
MR Active Time (Figure 4) 4 CK periods
t
MRIC
MR Inactive to first Control Port Access (Figure 4) 10 CK periods
t
MRSU
MR Setup Time to CK (Figure 4) 6 ns
t
MRH
MR Hold Time from CK (Figure 4) 2 ns
t
SISU
SI Setup Time to CK (Figure 5) 6 ns
t
SIH
SI Hold Time from CK (Figure 5) 2 ns
t
SIW
SI Pulse Width (Figure 5) 4 CK periods
DVGA Interface
t
STIW
A|BSTROBE Inactive Pulse Width (Figure 7) 2 CK periods
t
GSTB
A|BGAIN setup before A|BSTROBE (Figure 7) 6 ns
Parallel Output Interface
t
OENV
POUT_EN Active to POUT[15:0] Valid (Figure 9) 12 ns
t
OENT
POUT_EN Inactive to POUT[15:0] Tri-State (Figure 9) 10 ns
t
SELV
PSEL[2:0] to POUT[15:0] Valid (Figure 10) 13 ns
t
POV
RDY to POUT[15:0] New Value Valid (Note 5) (Figure 11) 7 ns
t
DBG
SCK to POUT[15:0], RDY, SFS, AOUT, BOUT Valid (Figure 12) 4 ns
Serial Interface
t
SFSV
SCK to SFS Valid (Note 3) (Figure 13) -2 1.6 3.5 ns
t
OV
SCK to A|BOUT Valid (Note 4) (Figure 13) -2 1.7 3.5 ns
t
RDYW
RDY Pulse Width (Figure 13) 2 CK periods
t
DCMSU
PSEL[2:0] Setup Time to SCK_IN (Figure 8) 3 1.4 ns
t
DCMH
PSEL[2:0] Hold Time from SCK_IN (Figure 8) 0.5 -0.9 ns
t
RDYV
SCK to RDY valid (Figure 13) -3 1.8 4 ns
JTAG Interface
t
JPCO
Propagation Delay TCK to TDO (Figure 14) 25 ns
t
JSCO
Propagation Delay TCK to Data Out (Figure 14) 35 ns
t
JPDZ
Disable Time TCK to TDO (Figure 14) 25 ns
t
JSDZ
Disable Time TCK to Data Out (Figure 14) 35 ns
t
JPEN
Enable Time TCK to TDO (Figure 14) 0 25 ns
t
JSEN
Enable Time TCK to Data Out (Figure 14) 0 35 ns
t
JSSU
Setup Time Data to TCK (Figure 14) 10 ns
t
JPSU
Setup Time TDI, TMS to TCK (Figure 14) 10 ns
t
JSH
Hold Time Data to TCK (Figure 14) 45 ns
t
JPH
Hold Time TCK to TDI, TMS (Figure 14) 45 ns
(1) Timing specifications are tested at TTL logic levels, V
IL
= 0.4V for a falling edge and V
IH
= 2.4V for a rising edge.
(2) Typical figures are at T
A
= 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured. Test Limits are specified to TI's AOQL (Average Outgoing Quality Level).
10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LM97593