LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 LM97593 Dual ADC / Digital Tuner / AGC Check for Samples: LM97593 FEATURES DESCRIPTION • • The LM97593 Dual ADC / Digital Tuner / AGC IC is a two channel digital downconverter (DDC) with integrated 12-bit analog-to-digital converters (ADCs) and automatic gain control (AGC). The LM97593 further enhances TI’s Diversity Receiver Chipset (DRCS) by integrating a wide-bandwidth dual ADC core with the DDC.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com Block Diagram 1 LM97593 CLC5526 (x2) SCK_IN LC 12 SerialOutA/B ADC DVGA IF A SerialOutB SCK 8 Dual Digital Tuner/AGC 12 ADC DVGA IF B SFS RDY ParallelOutput[15:0] LC ParallelOutputEnable CLK ParallelSelect[2:0] Figure 1.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 Block Diagram 2 AGAIN[2:0] ASTROBE 12 VINA ADC_A MUX A 14 Channel A Tuning, Channel Filters, and AGC Output Formatter SCK_IN AOUT/BOUT BOUT SCK SFS RDY VINB 12 MUX B ADC_B 14 Channel B Tuning, Channel Filters, and AGC POUT[15:0] PSEL[2:0] POUT_EN BSTROBE BGAIN[2:0] TEST_REG Figure 3. LM97593 Block Diagram PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. 80 Symbol SCK 99 SCK_IN 81 SFS 84, 86:88, 90, 91, 93:97, 104:106, 108, 109 POUT[15:0] Equivalent Circuit Description Output SERIAL DATA CLOCK, Active high or low The serial data is clocked out of the chip by this clock. The active edge of the clock is user programmable. This pin is tri-stated at power up and is enabled by the SOUT_EN control register bit.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. Symbol Equivalent Circuit Description 60 CE Input CHIP ENABLE. Active low This control strobe enables the read or write operation. The contents of the register selected by A[7:0] will be output on D[7:0] when RD is low and CE is low. If WR is low and CE is low, then the selected register will be loaded with the contents of D[7:0]. 116 TDO Output TEST DATA OUT.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) ADC Analog, Digital and IO Supply Voltages (VA, VD and VDR) −0.3V to 4.2V Difference between VA, VD, and VDR ≤ 100 mV Positive Core Supply Voltage (VD18) −0.3V to 2.35V −0.3V to (VDR +0.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 LM97593 Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = D18GND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, Internal VREF = +1.0V, fCLK = 65 MHz, VCM = VCOM, tR = tF = 1 ns, CL = 5 pF/pin. The ADC’s 11 most significant bits observed at the mixer output debug tap with NCO = 0Hz. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com LM97593 Electrical Characteristics (continued) Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = D18GND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, Internal VREF = +1.0V, fCLK = 65 MHz, VCM = VCOM, tR = tF = 1 ns, CL = 5 pF/pin. The ADC’s 11 most significant bits observed at the mixer output debug tap with NCO = 0Hz. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 LM97593 Electrical Characteristics (continued) Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = D18GND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, Internal VREF = +1.0V, fCLK = 65 MHz, VCM = VCOM, tR = tF = 1 ns, CL = 5 pF/pin. The ADC’s 11 most significant bits observed at the mixer output debug tap with NCO = 0Hz. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = D18GND = 0V, VA = VD = VDR = +3.3V (±10%), VD18 = +1.8V (±10%), Internal VREF = +1.0V, fCLK = 65 MHz, VCM = VCOM, tR = tF = 1 ns, CL = 5 pF/pin. CIC Decimation = 48, F2 Decimation = 2. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 AC Electrical Characteristics (continued) Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = D18GND = 0V, VA = VD = VDR = +3.3V (±10%), VD18 = +1.8V (±10%), Internal VREF = +1.0V, fCLK = 65 MHz, VCM = VCOM, tR = tF = 1 ns, CL = 5 pF/pin. CIC Decimation = 48, F2 Decimation = 2. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com Figure 8. LM97593 Dual Chip Mode Timing POUT_EN tOENV tOENT POUT[15:0] Figure 9. LM97593 Parallel Output Enable Timing n POUT_SEL[2:0] n+1 n+2 tSELV POUT[15:0] output (n) output (n+1) output (n+2) Figure 10. LM97593 Parallel Output Select Timing RDY RDY_POL = 0 RDY RDY_POL = 1 tPOV POUT[15:0] old output new output Figure 11. LM97593 Parallel Output Data Ready Timing SCK_IN tDBG POUT[15:0], AOUT, BOUT, RDY and SFS Figure 12.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 Figure 13. LM97593 Serial Port Timing TCK tJPCO tJPDZ tJPEN TDO tJCH tJCL TCK tJPSU tJPH TDI, TDS TCK tJSCO tJSDZ tJSEN Data Out TCK tJSSU tJSH Data In Figure 14.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com Figure 15.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 ADC Typical Performance Characteristics DNL, INL Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, PD = 0V, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 12 MHz, AIN = 0dBFS, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C DNL INL Figure 16. Figure 17.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com ADC Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, PD = 0V, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 249 MHz, AIN = -9dBFS, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C 16 SNR, SINAD, SFDR vs. VSUPPLY Distortion vs. VSUPPLY Figure 18.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 ADC Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, PD = 0V, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 249 MHz, AIN = -9dBFS, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C SNR, SINAD, SFDR vs.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com ADC Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, PD = 0V, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 249 MHz, AIN = -9dBFS, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C 18 Distortion vs.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 ADC Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, PD = 0V, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 249 MHz, AIN = -9dBFS, CL = 10 pF/pin, Duty Cycle Stabilizer On.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com CIC Output Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, PD = 0V, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 249 MHz, AIN = -9dBFS, CL = 10 pF/pin, Duty Cycle Stabilizer On.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 CIC Output Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, PD = 0V, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 249 MHz, AIN = -9dBFS, CL = 10 pF/pin, Duty Cycle Stabilizer On.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com DDC Output Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, PD = 0V, CIC decimation = 8, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 249 MHz, AIN = -9dBFS, CL = 10 pF/pin, Duty Cycle Stabilizer On.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 DDC Output Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, VA = VD = VDR = +3.3V, VD18 = +1.8V, PD = 0V, CIC decimation = 8, Internal VREF = +1.0V, fCLK = 65 MHz, fIN = 249 MHz, AIN = -9dBFS, CL = 10 pF/pin, Duty Cycle Stabilizer On.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION Figure 57. LM97593 Dual ADC / Digital Tuner / AGC Block Diagram with Control Register Associations The LM97593 contains two identical 12-bit ADCs driving the digital down-conversion (DDC) circuitry shown in the block diagram in Figure 57. ADC The ADCs operate off of a +3.3V supply and use a pipeline architecture with error correction circuitry to help ensure maximum performance.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 The frequencies, phase offsets, and phase dither of the two sine/cosine numerically controlled oscillators (NCOs) can be independently specified. Two sets of coefficient memories and a crossbar switch allow shared or independent filter coefficients and bandwidth for each channel. Both channels share the same decimation ratio and input/output formats.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com The nominal voltages for the reference bypass pins are as follows: VCOM = 1.5 V VRP = VCOM + VREF / 2 VRN = VCOM − VREF / 2 User choice of an on-chip or external reference voltage is provided. The internal 1.0 Volt reference is in use when the the VREF pin is connected to VA. If a voltage in the range of 0.8V to 1.2V is applied to the VREF pin, that is used for the voltage reference.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 Figure 59. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage equal to the reference voltage, VREF, be 180 degrees out of phase with each other and be centered around VCM. Single-Ended Operation Performance with differential input signals is better than with single-ended signals.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com The clock line should be terminated at its source in the characteristic impedance of that line. Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 (literature number SNLA035) for information on setting characteristic impedance. It is highly desirable that the the source driving the ADC CLK pin only drive that pin.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 DDC Application Information CONTROL INTERFACE The LM97593 is configured by writing control information into 237 control registers within the chip. The contents of these control registers and how to use them are described in Control Register Addresses and Defaults. The registers are written to or read from using the D[7:0], A[7:0], CE, RD and WR pins.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 Figure 61. Complex NCO Output Phase Dither Disabled Example of NCO spurs due to phase truncation (Before Phase Dithering) The LM97593 provides two sets of coefficient memory for both F1 and F2. These coefficient memories can be independently routed to channel A, channel B, or both channel A and B with a crossbar switch. The coefficients can be switched on the fly but some time will be required before valid output data is available.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com The 16 bit phase offset is set by loading the PHASE register according to the formula PHASE = 216P/2π, where P is the desired phase in radians ranging between 0 and 2π. PHASE is an unsigned 16-bit number. P ranges from 0 to 2π(1-2-16). Phase dithering can be enabled to reduce the spurious signals created by the NCO due to phase truncation. This truncation is unavoidable since the frequency resolution is much finer than the phase resolution.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 Figure 64. Complex NCO Output Phase Dither Enabled Worst Case Amplitude Spur, NCO at FS/8 The CIC filter has a gain equal to N4 (filter decimation^4) which must be compensated for in the “SHIFT UP” circuit shown in Figure 65 as well as Figure 60. This circuit has a gain equal to 2(SCALE-44), where SCALE ranges from 0 to 40. This circuit divides the input signal by 244 providing Figure 65.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com First Programmable FIR Filter (F1) The CIC/GAIN outputs are followed by two stages of filtering. The first stage is a 21 tap decimate-by-2 symmetric FIR filter with programmable coefficients. Typically, this filter compensates for a slight droop induced by the CIC filter while removing undesired alias images above Nyquist. In addition, it often provides stopband assistance to F2 when deep stop bands are required.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 Second Programmable FIR Filter (F2) The second stage decimate by two or four filter also uses externally downloaded filter coefficients. F2 determines the final channel filter response. The filter coefficients are 16-bit 2’s complement numbers. Unity gain will be achieved through the filter if the sum of the 63 coefficients is equal to 216. If the sum is not 216, then the F2 will introduce a gain equal to (sum of coefficients)/216.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com Figure 69. F2 GSM frequency response The complete channel filter response for standard coefficients is shown in Figure 70. Passband flatness is shown in Figure 71. The complete filter response for GSM coefficients is shown in Figure 72. GSM Passband flatness is shown in Figure 73. The mask shown in Figure 72 is derived from the ETSI GSM 5.05 specifications for a normal Basestation Transceiver (BTS).
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 Figure 71. CIC, F1, & F2 STD Passband Flatness Figure 72. CIC, F1, & F2 GSM frequency response This new decimation rate will maintain the same output bandwidth. The output bandwidth may only be changed in relation to the output sample rate by creating a new set of FIR filter coefficients. As the filter bandwidth decreases relative to the output sample rate, the CIC droop compensation performed by F1 may no longer be required. Figure 73.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com Overall Channel Gain The overall gain of the chip is a function of the amount of decimation (N), the settings of the “SHIFT UP” circuit (SCALE), the GAIN setting, the sum of the F1 coefficients, and the sum of the F2 coefficients. The overall gain is shown below in Equation 6. (6) Where: (7) and: (8) It is assumed that the DDC output words are treated as fractional 2’s complement words.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 Figure 74. LM97593 output circuit The channel outputs are accessible through serial output pins and a 16-bit parallel output port. The RDY pin is provided to notify the user that a new output sample period (OSP) has begun. OSP refers to the interval between output samples at the decimated output rate. For example, if the input rate (and clock rate) is 52 MHz and the overall decimation factor is 192 (N=48, F2 decimation=2) the OSP will be 3.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com Refer to Figure 13 for detailed timing information. Figure 75. Serial output formats Serial Outputs The LM97593 provides a serial clock (SCK), a frame strobe (SFS) and two data lines (AOUT and BOUT) to output serial data. The MUX_MODE control register specifies whether the two channel outputs are transmitted on two separate serial pins, or multiplexed onto one pin in a time division multiplexed (TDM) format.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 The serial outputs use the format shown in Figure 75. Figure 75(a) shows the standard output mode (the PACKED mode bit is low). The chip clocks the frame and data out of the chip on the rising edge of SCK (or falling edge if the SCK_POL bit in the input control register is set high).
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com Parallel Port Output Numeric Formats The I/Q samples can be rounded to 16 or 24 bits or the full 32 bit word can be read. By setting the word size to 32 bits it is possible to read out the top 16-bits and only observe the top 8 bits if desired. Additionally, the output samples can be formatted as floating point numbers with an 8-bit mantissa and a 4 bit exponent.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 Figure 78. AGC Setup AGC setpoint and deadband are illustrated in Figure 78. The loop time constant is a measure of how fast the loop will track a changing signal. Values down to approximately 1.0 microsecond will be stable with the second order LC noise filter. Since the DVGA operates with 6dB steps the deadband should always be greater than 6dB to prevent oscillation. An increased deadband value will reduce the amount of AGC operation.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com POWER MANAGEMENT The LM97593 can be placed in a low power (static) state by stopping the input clock and setting the PD pin high. To prevent this from placing the LM97593 into unexpected states, the SI pin of the LM97593 should be asserted prior to disabling the input clock and held asserted until the input clock has returned to a stable condition. TESTABILITY JTAG Boundary Scan The LM97593 supports IEEE 1149.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 SCK will be set to the proper strobe rate for each debug tap point. POUT_EN and PSEL[2:0] have no effect in Debug Mode. The outputs are turned on when the Debug Mode bit is set. Normal serial outputs are also disabled. CONTROL REGISTERS The chip is configured and controlled through the use of 8-bit control registers.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 Register Name PHASE_A FREQ_B Width 2B 4B Type R/W R/W www.ti.com Default (1) 0 0 Addr 11-12 13-16 Bit Description 7:0 Phase word for channel A. Format is a 16-bit, unsigned magnitude number spread across 2 registers. The LSBs are in the lower registers. The NCO phase PHI is PHI=2*pi*PHASE_A/ 216. 7:0 Frequency word for channel B. Format is a 32-bit, 2’s complement number spread across 4 registers. The LSBs are in the lower registers.
LM97593 www.ti.com Register Name SNWS019B – JULY 2007 – REVISED APRIL 2013 Width Type Default (1) Addr Bit Description Selects internal node tap for debug. 0 selects F1 output for BI, 20 bits 1 selects F1 output for BQ, 20 bits 2 selects F1 output for AQ, 20 bits 3 selects F1 output for AI, 20 bits 4 selects F1 input for BI, 20 bits 5 selects F1 input for BQ, 20 bits 6 selects F1 input for AI, 20 bits 7 selects F1 input for AQ, 20 bits 8 selects NCO A, cosine output. 17 bits, 3 LSBs are 0.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 AGC Theory of Operation A block diagram of the AGC is shown in Figure 81. The DVGA interface comprises four pins for each of the channels. The first three pins of this interface are a 3-bit binary word that controls the DVGA gain in 6dB steps (AGAIN). The final pin is ASTROBE which allows the AGAIN bits to be latched into the DVGA’s register.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com Refer to Figure 7 for detailed timing information. Figure 82. Timing diagram for AGC/DVGA interface, Channel A The “FIXED TO FLOAT CONVERTER” takes the fixed point 9-bit output from the CIC filter and converts it to a “floating point” number. This conversion is done so that the 32 values in the RAM can be uniformly assigned (dB scale) to detected power levels (54 dB range). This provides a resolution of 1.7dB between detected power levels.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 This equation assumes that the DVGA gain control polarity is positive as is the case for the CLC5526. The gain around the entire loop must be negative. Observe in Equation 10 that the control gain is dependent on operating point G. If we instead compute the control gain with log conversion then: (11) which is no longer operating-point dependent.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com 20 AGC RAM CONTENTS 0 -20 -40 -60 -80 -100 -120 0 5 10 15 20 25 30 ADDRESS Figure 83. Example of programmed RAM contents 20 AGC RAM CONTENTS 0 -20 -40 -60 -80 -100 -120 0 10 20 30 40 50 60 POUT (dB) Figure 84. Example of programmed RAM contents Table 5. 15-bit Mixer Output Alignment into the 22-bit SHIFT-UP Based On EXP AGAINa EXPb Inputc 21d 20 19 18 17 16 15 14 ...
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 The AGC may be forced to free run by setting AGC_HOLD_IC low. Writing an initial condition to AGC_IC_A|B and then setting AGC_HOLD_IC high will force the AGC to a fixed gain. The three MSBs of the value written to AGC_IC_A|B are inverted and output to drive the DVGA. Allowing the AGC to free run should be appropriate for most applications.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com FILTER COMPONENT VALUES FREQUENCY 150 MHz 250 MHz L1 43 nH 22 nH 18 pF 43 pF C1 18 pF 43 pF C2 0.5 pF C3 - 24 0.01 PF 0.1 PF 23 10 PF 22 0.1 PF 15 0.01 PF 0.1 PF 0.1 PF T3 M/A-COM PART NO. ETK4-2T VRNA 0.01 PF 1 nF C1B 500Ö 27 26 500Ö C2B 3 CLC5526 DVGA REMOVE GND & POWER PLANES FROM UNDER THESE COMPONENTS & SIGNALS AS MUCH AS POSSIBLE T3 M/A-COM PART NO. ETK4-2T VINBVINB+ LM97593 0.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise thus generated could have significant impact upon system noise performance.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com Figure 87. Isolating the ADC Clock from other Circuitry with a Clock Tree Common Application Pitfalls Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation.
LM97593 www.ti.com SNWS019B – JULY 2007 – REVISED APRIL 2013 Evaluation Hardware Evaluation boards are available to facilitate designs based on the LM97593: LM97593EB The LM97593 evaluation board provides a complete narrowband receiver from IF to digital symbols. SOFTWARE Control panel software for the LM97593 supports complete device configuration on both evaluation boards. Integrated capture software manages the capture of data and its storage in a file on a PC.
LM97593 SNWS019B – JULY 2007 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2013) to Revision B • 58 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2014 PACKAGING INFORMATION Orderable Device Status (1) LM97593VH/NOPB ACTIVE Package Type Package Pins Package Drawing Qty QFP NND 128 66 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 85 LM97593VH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PACKAGE OPTION ADDENDUM www.ti.
MECHANICAL DATA NND0128A VLA128A (Rev C) www.ti.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
