Datasheet

Digital Electrical Characteristics
Unless otherwise stated, the following conditions apply VIO = +3.3V, VDDA = VDDC = +1.8V, T
A
= 25°C.
Symbol Parameter Conditions Min Typ Max Unit
PLL DIFFERENTIAL REFERENCE CLOCK DC SPECIFICATIONS
V
ID
PLL Reference Clock
Differential Input Amplitude
AC Coupled to pins 13 & 14. 1B[0] = 0
(see (Note 2))
200 400 mV
V
ICM
PLL Reference Clock Input
Common Mode Voltage
Pins 13 & 14 bias voltage, VICM ≈ 0.5
X VDDA
0.9 V
R
IN
Single-ended Input
Resistance
11
kΩ
PLL 1.8V LVCMOS SINGLE-ENDED REFERENCE CLOCK DC SPECIFICATIONS
V
IH
LVCMOS Input “HI” Voltage Pin 13. Register 1B[0] = 1 1.5
V
V
IL
LVCMOS Input “LO”
Voltage
Pin 13. Register 1B[0] = 1 0.3
R
IN
LVCMOS Input Resistance Pin 13 = 0V or VIO 11
kΩ
3.3V I/O DC SPECIFICATIONS
V
IH
Logic Input “HI” Voltage 2.2
V
V
IL
Logic Input “LO” Voltage 0.5
I
IN-H/L
Input Current −1 1 µA
V
OH
Logical Output “HI” Voltage I
OH
= 2 mA 2.9
V
V
OL
Logical Output “LO” Voltage I
OL
= 2 mA 0.34
I
O-H/L
Logic Output Current ±10 mA
Serial Interface Timing Characteristics
Unless otherwise stated, the following conditions apply VIO = +3.3V, VDDA = VDDC = +1.8V, T
A
= 25°C.
Symbol Parameter Conditions Min Typ Max Units
t
LES
sLE Setup Time 1.4
ns
t
LEH
sLE Hold Time 1.9
t
LEHI
sLE HI Time 2.4
t
WS
sWR Setup Time 1.4
t
WH
sWR Hold Time 2.4
t
RS
sRD Data Valid Setup Time 6.3
t
RH
sRD Data Valid Hold Time 6.2
t
SCLKR
sCLK Rise Time 1.7
ns
t
SCLKF
sCLK Fall Time 1.7
t
SCLKH
sCLK High Time 2.4
ns
t
SCLKL
sCLK Low Time 3.4
f
SCLK
sCLK Frequency 80 MHz
Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
can or should be operated at these limits.
Operating Ratings indicate conditions for which the device is guaranteed to be functional, but do not guarantee specific performance limits. Guaranteed speci-
fications and test conditions are specified in the Electrical Characteristics section. Operation of the device beyond the Operating Ratings is not recommended as
it may degrade the lifetime of the device.
Note 2: The combination of common mode and voltage swing on the clock input must ensure that the positive voltage peaks are not above VDDA and the negative
voltage peaks are not below AGND.
Note 3: The maximum power dissipation is a function of T
JMAX
, θ
JA
and T
A
. The maximum allowable power dissipation at any ambient temperature is
P
D
= (T
JMAX
- T
A
)/ θ
JA
. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow.
Note 4: Human Body Model, applicable std. JESD22–A114–C. Machine Model, applicable std. JESD22–A115–A. Field induced Charge Device Model, applicable
std. JESD22–C101–C.
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LM96570