Datasheet

Pin Descriptions
Pin No. Name Type Function and Connection
1 – 4, 21 – 32 P0-7, N0-7 Output
Control signals for pulser. P outputs control positive pulses and N outputs
control negative pulses. See logic Table 1.
13 PLL_CLK+ Input
PLL Reference Clock PLUS Input, LVDS compatible or Single-Ended LV
CMOS input, programmable through 4-Wire Serial Interface (Register
1Bh[0])
14 PLL_CLK- Input
PLL Reference Clock MINUS input, LVDS compatible. For Single-Ended
PLL Reference Clock operation, tie this pin to AGND or VDDA.
7 TX_EN Input
1 = Beamformer starts firing
0 = Beamformer ceases firing
16 PLL_Vin Input
Voltage range 0.8-1.2V for tuning internal PLL noise performance. Under
normal conditions, 0.94V is recommended.
17
PLL_Iin
Input
100 μA current input
8 RST Input
Asynchronous Chip Reset
1 = Reset
0 = No Reset
12 sCLK Input 4-Wire Serial Interface Clock
10 sLE Input 4-Wire Serial Interface Latch Enable
11 sWR Input 4-Wire Serial Interface Data Input for writing data registers
9 sRD Output 4-Wire Serial Interface Data Output for reading data registers
15 VDDA Power Analog supply voltage (1.8V)
6 VDDC Power Digital core supply voltage (1.8V)
19 VIO Power Digital I/O supply voltage (2.5 to 3.3V)
0, 18 AGND Ground PLL Analog ground
5 DGND Ground Digital core ground
20 DGNDIO Ground Digital I/O ground
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LM96570