Datasheet
STEP 3.
•
When the write operations are complete and the TX path is ready, pull “TX_EN“ high. After 6 ICLK (160MHz) cycles (37.5 ns)
have passed, each channel will start to count its programmed delay profile. When it reaches the preset value, it will trigger the
firing sequence. TX_EN should always remain high during the firing operation. See Figure 12 for the firing diagram.
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FIGURE 17. Beamformer Output in CW Mode
Example 3 (Invert Firing Mode)
Example 3 demonstrates the invert firing mode, which is used for harmonic imaging. In invert firing mode, each TX transmission
consists of two firings. First, the preloaded pulse pattern will be fired directly (non-inverted). After RX is completed, in the subsequent
firing, the same pulse pattern will be inverted and fired again. In this example, all Channels have zero delay, and have the same
have the same unit pulse width of 50ns. The 1st firing is a non-inverted firing, in which the P pattern is “01101001” and the N pattern
is “10010110”. See Figure 18 for the firing diagram.
STEP 1.
•
Write to Register 1Ah to configure the pulse pattern length, pulse output frequency, and enable PLL. Based on the Register
Definition in Table 4, here Register 1Ah (14-bit) = 0011 000 1000 001 b
RESERVED 0 reserved bit is kept at “0”
CW 0 beamformer is NOT in the CW firing mode
INV_FIRE_EN 1 beamformer is in the “invert firing” mode
PLL_EN 1 PLL is enabled
FREQ_DIV 000 1000 pulse width is one period of 1/8 of the master clock frequency (160MHz / 8 = 20MHz,
i.e. 50ns period)
PAT_LEN 001 pulse pattern length is 8 bits
STEP 2.
Write the delay profile to each Channel. The duty-cycle control feature is disabled.
Channel Register Data Fire Delay
Ch 0 - 7 Reg. 00h - 07h 00 000 00000000000000 000 b no delay
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LM96570