Datasheet
Channel Register Data Programmed
Fire Delay
Actual Fire
Delay*
P to N Delay & P's Pulse Width
Ch 6 Reg. 06h 10 101 00000000001100 110 b 12CD + 6FD
P: 13CD + 5FD P fires 7FDs later than N. P's
pulse width is smaller than N by
14FDs.
N: 12CD + 6FD
Ch 7 Reg. 07h 00 111 00000000001110 111 b 14CD + 7FD
N: 14CD + 7FD
P fires at the same time as N. P's
pulse width is the same as N.
P: 14CD + 7FD
* These delays do not include the internal propagation delay relative to the TX_EN rising edge. See Beamformer Output Timing Characteristics.
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FIGURE 16. Beamformer Output with Pulse Width Adjustment
Example 2 (CW Mode)
In Example 2, the ultrasound system is in CW mode, in which a [1 0] pulse sequence for the P part and a [0 1] pulse sequence for
the N part are continuously fired at a frequency of 10 MHz. In CW mode, these P part and N part pulse sequences are fixed
at pre-set default patterns, and their registers Reg. 18h and Reg. 19h CANNOT be written to. The delay profile of each
Channel is the same as in example 1. In CW mode, the pulse pattern will be fired in a circular fashion. After the last bit of the pulse
pattern, the 1st bit will follow it immediately, thus configuring the pulse pattern with infinite or continuous pulse length.
STEP 1.
•
Write to Register 1Ah to configure the pulse pattern length, pulse output frequency, and enable PLL. Based on the Register
Definition in TOP CONTROL REGISTER, here Register 1Ah (14-bit) = 0101 000 1000 000 b.
RESERVED 0 reserved bit is kept at “0”
CW 1 beamformer is in the CW firing mode
INV_FIRE_EN 0 beamformer is NOT in the “invert firing” mode
PLL_EN 1 PLL is enabled
FREQ_DIV 000 1000 pulse width is one period of 1/8 of the master clock frequency (160MHz / 8 = 20MHz,
i.e. 50ns period)
PAT_LEN 0 pulse pattern length is 4 bits, as 4 bits fired circularly is sufficient to generate a CW
waveform.
STEP 2.
•
The delay profile in example 2 is the same as in example 1A. If the beamformer is not powered down, the delay profile will be
retained in the on-chip registers. Here, if the firing of example 2 immediately follows example 1A, the delay profile does not
need to be written again.
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LM96570