Datasheet

STEP 2.
•
Write the delay profile to each Channel (Registers 00-07h) with the following 22-bit data. The write timing diagram is similar to
that shown in Figure 14, except for the register addresses and the 22-bit data depths.
Channel Register Data Fire Delay
Ch 0 Reg. 00h 00 000 00000000000000 000 b no delay
Ch 1 Reg. 01h 00 000 00000000000010 001 b 2 coarse delays + 1 fine delay
Ch 2 Reg. 02h 00 000 00000000000100 010 b 4 coarse delays + 2 fine delay
Ch 3 Reg. 03h 00 000 00000000000110 011 b 6 coarse delays + 3 fine delay
Ch 4 Reg. 04h 00 000 00000000001000 100 b 8 coarse delays + 4 fine delay
Ch 5 Reg. 05h 00 000 00000000001010 101 b 10 coarse delays + 5 fine delay
Ch 6 Reg. 06h 00 000 00000000001100 110 b 12 coarse delays + 6 fine delay
Ch 7 Reg. 07h 00 000 00000000001110 111 b 14 coarse delays + 7 fine delay
STEP 3A.
•
Write the pulse pattern to each Channel (Registers 08h to 0Fh for P and 10h to 17h for N) with the following 64 bits of data
(shown in hexadecimal format). The write timing diagram is similar to Figure 14 except for the register addresses and the 64-
bit data depths.
Channel Register Data
P part Ch 0 - 7 Reg. 08h - 0Fh 5555 5555 5555 5555 h
N part Ch 0 - 7 Reg. 10 - 17h AAAA AAAA AAAA AAAA h
STEP 3B (OPTIONAL instead of STEP 3A).
•
Since these 8 channels have the same pulse pattern, we can also directly write to Register 18h (P part of pulse pattern) and
Register 19h (N part of pulse pattern) instead of writing the same pulse pattern to each individual channel 8 times. Therefore
step 3a can be replaced by step 3b.
•
Write the pulse pattern to Register 18h and Registers 19h. The write timing diagram is similar to Figure 6, except for the register
addresses and the 64-bit data depths.
Channel Register Data
P part Ch 0 - 7 Reg. 18h 5555 5555 5555 5555 h
N part Ch 0 - 7 Reg. 19h AAAA AAAA AAAA AAAA h
STEP 4.
•
When the write operations are complete and the TX path is ready, pull “TX_EN “ high.
•
After 6 ICLK (160MHz) cycles (37.5ns) have passed, each Channel will start to count its programmed delay profile. When it
reaches the preset value, it will trigger the firing sequence. Channel 0 with no delay fires first and is followed by Channel 1 after
2 coarse delays plus one fine delay (13.28ns). Each bit of the 64-bit pulse pattern is continuously fire from LSB to MSB until all
64 bits are output. “TX_EN” should always remain high during a firing operation.
•
After firing is complete for all channels, “TX_EN” is pulled low, as the beamformer waits for the next firing signal, i.e., when
“TX_EN” is pulled high. See Figure 15 for firing diagram.
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LM96570