Datasheet

Bit(s) Description

IFE: Invert Fire Enable. This bit enables the Invert Fire Mode, which is used for harmonic imaging.

0 Invert Fire Mode Disabled. The programmed pulse pattern will be fired directly.

1 Invert Fire Mode Enabled. Each TX transmission will consist of two firings. First, the

programmed pulse pattern will be fired directly (non-inverted). Second, after RX is completed,

the pulse pattern will be inverted and fired again. During “invert firing” mode, there should

be no write or read-back activity on the serial interface lines and the user must ensure

that the sLE line remains high to prevent the invert-firing from inadvertently resetting.

PLLE: PLL Enable. This bit enables the on-chip PLL

0 PLL Disabled

1 PLL Enabled

9:3

FD: Frequency Division. These bits determine the pulse width of each bit in the non-return zero output pulse

pattern. The decimal value of these bits correspond to the 2X division factor between the 160 MHz master

clock and the output pulse frequency a one-high-one-low pattern. For example, when the desired output

frequency is 160 MHz / 2 = 80 MHz, then FD = 2 and Register 1Ah[9:3] = 000 0001. If the desired output

frequency is 160 MHz / 32 = 5MHz, then FD = 32 and Register 1Ah[9:3] = 001 0000. If the desired output

frequency is 160 MHz / 256 = 0.625 MHz, then FD = 256, which is the Maximum, and Register 1Ah[9:3] =

000 0000.

2:0

PL: Pattern Length. These bits determine the length of the pulse pattern for all channels. The pulse pattern

length set in this register must coincide exactly with the actual pattern programmed to registers 08h through

17h, or registers 18h and 19h. For example, if the pattern length is set in this register to be 24 pulses, then

exactly, a 24-bit value must be written into registers 08h through 17h or registers 18h and 19h. If a different

number of bits/pulses is programmed into those registers, the outputs will not function correctly.

000 4-pulse pattern length. Registers 08h to 19h will have a 4-bit depth.

001 8-pulse pattern length. Registers 08h to 19h will have an 8-bit depth.

010 16-pulse pattern length. Registers 08h to 19h will have a 16-bit depth.

011 24-pulse pattern length. Registers 08h to 19h will have a 24-bit depth.

100 32-pulse pattern length. Registers 08h to 19h will have a 32-bit depth.

101 40-pulse pattern length. Registers 08h to 19h will have a 40-bit depth.

110 48-pulse pattern length. Registers 08h to 19h will have a 48-bit depth.

111 64-pulse pattern length. Registers 08h to 19h will have a 64-bit depth.

PLL CLOCK INPUT SELECTION REGISTER

Address: 1Bh

b[7:1] b[0]

Description RSV PLLCK

0Bh Default 0 0 0 0 0 0 0 0

Bit(s) Description

7:1 RSV: Reserved. This is a reserved bit. When writing to Register 1Bh, keep this bit at “0.”

PLLCK: PLL Clock. This bit determines whether the PLL input clock is to be a single-ended LVCMOS input

or a differential input.

0 Differential PLL Clock Input.

1 LV CMOS PLL Clock Input.

www.national.com 20

LM96570