Datasheet

Bit(s) Description
2:0
FDA: Fine Delay Adjust. These 3 bits set the clock phase for the 14-bit programmable counter, which
in turn control the fractional amount of delay in increments of 1/8 for the P/N outputs relative to the
internal Fire signal.
Again, this is not to be confused with the delays associated with Pulse Width Adjustment, which involves
delaying the P outputs relative to the N output. Fine Delay Adjustment involves delaying the firing of
both P/N outputs relative to the internal Fire signal.
In addition to the number of ICLK cycle delays determined by the Coarse Delay Adjust, the P/N outputs
can be delayed further by the following number of fractional ICLK cycle delays:
000 0° or 0 ICLK cycle
001 45° or 1/8 ICLK cycle
100 90° or 2/8 ICLK cycle
011 135° or 3/8 ICLK cycle
100 180° or 4/8 ICLK cycle
101 225° or 5/8 ICLK cycle
110 270° or 6/8 ICLK cycle
111 315° or 7/8 ICLK cycle
INDIVIDUAL CHANNEL (0 to 7) “P” PART PULSE REGISTERS
Address: 08h to 0Fh
Registers 08h to 0Fh control the individual pulse patterns for channels 0 to 7, respectively.
b[63:0], b[63:16], b[63:24], b[63:32], b[63:40], b[63:48], b[63:56], or b[63:60]
Description PPP
08-0Fh Default 5555 5555 5555 5555 h
Bit(s) Description
63:0,
63:16,
63:24,
63:32,
63:40,
63:48,
63:56,
63:60
PPP: “P” Part Pulse Pattern. These bits in registers 08h to 0Fh determine the “P” part pulse pattern for
channels 0 to 7, respectively. Each bit represents one pulse, thus the full bit stream of each register is
equivalent to one full length pulse pattern. Upon firing, the LSB is sent out first. The register's bit depth or
pulse pattern length may be 64, 48, 40, 32, 24, 16, 8, or 4, depending on the value of Register 0Ah[2:0]. By
default, the pulse pattern length is 64 bits deep, and the bit stream or pulse pattern is 5555 5555 5555 5555
h.
INDIVIDUAL CHANNEL (0 to 7) “N” PART PULSE REGISTERS
Address: 10h to 17h
Registers 10h to 17h control the individual pulse patterns for channels 0 to 7, respectively.
b[63:0], b[63:16], b[63:24], b[63:32], b[63:40], b[63:48], b[63:56], or b[63:60]
Description NPP
10-17h Default AAAA AAAA AAAA AAAA h
Bit(s) Description
63:0,
63:16,
63:24,
63:32,
63:40,
63:48,
63:56,
63:60
NPP: “N” Part Pulse Pattern. These bits in registers 10h to 17h determine the “N” part pulse pattern for
channels 0 to 7, respectively. Each bit represents one pulse, thus the full bit stream of each register is equivalent
to one full length pulse pattern. Upon firing, the LSB is sent out first. The register's bit depth or pulse pattern
length may be 64, 48, 40, 32, 24, 16, 8, or 4, depending on the value of Register 0Ah[2:0]. By default, the pulse
pattern length is 64 bits deep, and the bit stream or pulse pattern is AAAA AAAA AAAA AAAA h.
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LM96570