Datasheet

INDIVIDUAL CHANNEL (0 to 7) DELAY PROFILE REGISTERS

Address: 00h to 07h

Registers 00h to 07h control the individual delay profile and Pulse Width adjustments for channels 0 to 7, respectively.

b[21:20] b[19:17] b[16:3] b[2:0]

Description PWAE PWA CDA FDA

00h Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

01h Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1

02h Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0

03h Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1

04h Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0

05h Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1

06h Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0

07h Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1

Bit(s) Description

21:20

PWAE: Pulse Width Adjust Enable.

00 Pulse Width Adjustment Disabled, i.e., each channel’s P and N outputs are latched out by the

same clock.

01 N Output Pulse Width Adjustment Enabled, i.e., the N outputs are latched out by a clock with

a different phase from that of the P outputs. The clock used for the N output is phase delayed

relative to the one for the P output, and thus, N is delayed relative to P. As a result, because

the P and N outputs never overlap, N’s pulse width is smaller than P’s.

10 P Output Pulse Width Adjustment Enabled, i.e., the P outputs are latched out by a clock with a

different phase from that of the N outputs. The clock used for the P output is phase delayed

relative to the one for the N output, and thus, P is delayed relative to N. As a result, because

the P and N outputs never overlap, P’s pulse width is smaller than N’s.

11 Pulse Width Adjustment Disabled, i.e., each channel’s P and N outputs are latched out by the

same clock.

19:17

PWA: Pulse Width Adjust. These 3 bits control the amount of phase delay of the clock that latches out

the pulse width adjusted output relative to the unadjusted output. For example, if Pulse Width Adjust is

enabled for the P outputs, then these 3 bits will determine the alternative clock phase that latches out

the P output

16:3

CDA: Coarse Delay Adjust. Coarse delay is generated by a 14-bit programmable counter. These 14

bits control the number of internal clock cycles (0 to 16,384) that the P/N outputs are delayed relative

to the internal Fire signal.

This is not to be confused with the delays associated with Pulse Width Adjustment, which involves

delaying the P outputs relative to the N output. Coarse Delay Adjustment involves delaying the firing of

both P/N outputs relative to the internal Fire signal.

The delay between when the user applies the TX_EN signal and when the P/N outputs are sent out =

[internal propagation delay + # of ICLK cycles determined by the Coarse Delay Adjust value + # of

fractional ICLK cycles determined by the Fine Delay Adjust value.] See the section on “Fire Delay” within

the Functional Description for more details.

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LM96570