Datasheet

TABLE 3. Register Map
Address Number of Bits Default Value (binary / hex)
Individual Channel (0 to 7) Delay and Pulse Width Profile Registers
00h
22
00 000 00000000000000 000 b
01h 00 000 00000000000010 001 b
02h 00 000 00000000000100 010 b
03h 00 000 00000000000110 011 b
04h 00 000 00000000001000 100 b
05h 00 000 00000000001010 101 b
06h 00 000 00000000001100 110 b
07h 00 000 00000000001110 111 b
Individual Channel (0 to 7) “P” Part Pulse Pattern Registers
08h
4, 8, 16, 24, 32, 40, 48, or 64* 5555 5555 5555 5555 h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Individual Channel (0 to 7) “N” Part Pulse Pattern Registers
10h
4, 8, 16, 24, 32, 40, 48, or 64* AAAA AAAA AAAA AAAA h
11h
12h
13h
14h
15h
16h
17h
ALL Channels “P” Part Pulse Pattern Register
18h 4, 8, 16, 24, 32, 40, 48, or 64* 5555 5555 5555 5555 h
ALL Channels “N” Part Pulse Pattern Register
19h 4, 8, 16, 24, 32, 40, 48, or 64* AAAA AAAA AAAA AAAA h
Top Control Register
1Ah 14 0001 0001111 111 b
PLL Input Clock Selection Register
1Bh 8 0000 0000 b
* The bit depth of registers 08h to 19h may range from 4 to 64 bits depending on the pattern length value that is programmed in Register 1Ah[2:0].
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LM96570