Datasheet

tp1=tp2. (See the right half of Figure 8.) Since Pn and Nn and
low-voltage signals, it is much easier to control their timing.
After such pulse width adjustments are made, the output of
the pulser will have the desired duty cycle.
30129707
FIGURE 8. Duty Cycle Adjustment
Pulse Width Adjustment is achieved indirectly by exploiting
the fact that the P and N pulses never overlap and by manip-
ulating the phase delays of the P and N outputs relative to
each other. For example, delaying P relative to N will reduce
the pulse width of P and increase the pulse width of N. Simi-
larly, delaying N relative to P will reduce the pulse width of N
and increase the pulse width of P. Thus, adjusting the relative
P to N phase delay essentially has the effect of adjusting the
P and N pulse widths.
Bits 20 and 21 of Registers 00h to 07h enable the Pulse Width
Adjustment feature and also specify which output (P or N) is
to be phase delayed relative to the other according to the fol-
lowing table:
00-7h[21:20]
00 Pulse Width Adjustment Disabled, i.e., each channel's P and N outputs are latched out by the same
clock.
01 N Output Pulse Width Adjustment Enabled, i.e., N is delayed, while P remains undelayed. As a result,
because the P and N outputs never overlap, N's pulse width decreases, while P's pulse width increases.
10 P Output Pulse Width Adjustment Enabled, i.e., P is delayed, while N remains undelayed. As a result,
because the P and N outputs never overlap, P's pulse width decreases, while N's pulse width increases.
11 Pulse Width Adjustment Disabled, i.e., each channel's P and N outputs are latched out by the same
clock.
Bits 17 to 19 of Registers 00h to 07h determine the amount
of relative P to N phase delay, and vice-versa. These 3 bits
(00-07h[19:17]) set the alternative clock phase by which the
output (P or N) will lag. For example, if P Pulse Width Adjust
is enabled for Channel 1 (00h[21:20] = “10”), then the 3 bits
(00h[19:17]) set the alternative clock phase by which the P
output will lag relative to the N output, which clock phase is
still set by 00h[2:0].
The pulse width adjusted output is delayed relative to the oth-
er output according to the following phase angle / internal
clock fractional step diagram. The relative delay, t
RD
, is de-
termined by phase lag of the alternative clock phase with
reference to the original clock phase set by bits 0 to 2. If bits
17 to 19 are the same as bit 0 to 3, the relative delay is 360°,
which is equivalent to one step of coarse delay, i.e. t
RD
is one
system clock period, 6.25ns.
30129714
FIGURE 9. Pulse Width Adjustment (00–07h[19:17])
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