Datasheet

30129714
FIGURE 5. Fine Delay Adjustment (00–07h[2:0])
in 1/8 Internal Clock Phase Angle Steps
Since an internal clock cycle is 6.25 ns, the total 17-bit user-
programmable delay ranges from 0 up to approximately
102.4μs.
The following example illustrates a 64-bit pulse pattern with
various delay profiles. Here, the user-programmable pulse
output frequency is 10 MHz. The delays are programmed
such that the delay between adjacent channels is approxi-
mately 13.28 ns, which is 2 coarse delays plus one fine delay
(1 coarse step or internal clock cycle = 6.25 ns & 1 fine step
or 1/8 internal clock cycle = 0.78 ns).
Ch. Register Data Fire Delay
Ch 0 Reg. 00h 00 000 00000000000000 000 b no user-programmed delay
Ch 1 Reg. 01h 00 000 00000000000010 001 b 2 coarse delays + 1 fine delay
Ch 2 Reg. 02h 00 000 00000000000100 010 b 4 coarse delays + 2 fine delay
Ch 3 Reg. 03h 00 000 00000000000110 011 b 6 coarse delays + 3 fine delay
Ch 4 Reg. 04h 00 000 00000000001000 100 b 8 coarse delays + 4 fine delay
Ch 5 Reg. 05h 00 000 00000000001010 101 b 10 coarse delays + 5 fine delay
Ch 6 Reg. 06h 00 000 00000000001100 110 b 12 coarse delays + 6 fine delay
Ch 7 Reg. 07h 00 000 00000000001110 111 b 14 coarse delays + 7 fine delay
Here, the pulse pattern may be programmed to each individ-
ual channel via Registers 08h to 0Fh for the P channels and
10h to 17h for the N channels with the following 64 bits of data
(shown in hexadecimal format).
Channel Register Data
P part Ch 0 - 7 Reg. 08h - 0Fh 5555 5555 5555 5555 h
N part Ch 0 - 7 Reg. 10h - 17h AAAA AAAA AAAA AAAA h
Alternatively, since these 8 channels have the same pulse
patterns, they can also be programmed directly to Register
18h (P part of pulse pattern ) and Register 19h (N part of pulse
pattern) instead of writing the same pulse pattern to each in-
dividual channel 8 times.
Channel Register Data
P part Ch 0 - 7 Reg. 18h 5555 5555 5555 5555 h
N part Ch 0 - 7 Reg. 19h AAAA AAAA AAAA AAAA h
Figure 6 shows the Beamformer channel outputs and TX_EN
timing. After the internal propagation delay has elapsed, each
channel counts its programmed delay value. When it reaches
this value, it will transmit the programmed pulse pattern.
Channel 0, which has no user-programmed delay, outputs
first and then is followed by Channel 1 after 2 coarse delays
plus one fine delay (13.28 ns). Each bit of the 64-bit register’s
pulse pattern is continuously transmitted from its LSB to MSB
until all 64 bits are output.
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