Datasheet

Functional Description
P/N OUTPUT PATTERN PROGRAMMING
The output pulse pattern for each of the 8 P channels is set
by programming registers 08h to 0Fh, respectively. The out-
put pulse pattern for each of the 8 N channels is set by
programming registers 10h to 17h, respectively. Program-
ming each bit of these registers yields P/N output pulses
according to Table 1. Each bit represents one pulse, thus the
full bit stream of each register is equivalent to one full length
pulse pattern. However, note that the LSB of the register is
transmitted as an output pulse first and the MSB is transmitted
as an output pulse last. For example: a register value of
“10110100” will yield an output pulse pattern versus time such
as “00101101”.
TABLE 1. Truth Table — Beamformer Output-to-Pulser Output
P Pattern Register Bit
Value
N Pattern Register Bit
Value
Beamformer P Output Beamformer N
Output
Pulser Output
0 0 0 0 0
1 0 1 0 VPP − 0.7V
0 1 0 1 VNN + 0.7V
1 1 0 0 0
If the user wishes to program the same pulse pattern for all 8
P channels or all 8 N channels, there are two additional “global
channel” registers available for ease and convenience. Pro-
gramming a pulse pattern via Register 18h will internally apply
the same pulse pattern to all 8 P channels Similarly, program-
ming a pulse pattern via Register 19h will internally apply the
same pulse pattern to all 8 N channels.
These bit depths of these registers, i.e., pulse pattern lengths,
are user-programmable via bits 0 to 2 of Register 1Ah. These
3 bits (1Ah[2:0]) determine the bit depth or pulse pattern ac-
cording to Table 2. The outputs will not function correctly if a
different number of bits, inconsistent with what is set by Reg-
ister 1Ah[2:0], is programmed into any of the registers, 08h to
19h.
TABLE 2. Pulse Pattern Length Truth Table
1Ah[2:0] Registers 08h to 19h Bit Depth Pulse Pattern Length
000 4 bits 4 pulses
001 8 bits 8 pulses
010 16 bits 16 pulses
011 24 bits 24 pulses
100 32 bits 32 pulses
101 40 bits 40 pulses
110 48 bits 48 pulses
111 64 bits 64 pulses
DELAY ADJUSTMENT
The delay between the rising edge of the TX_EN signal and
the first programmed P/N output pulse typically consists of:
(1) an internal propagation delay relative to the TX_EN rising
edge plus (2) a user-programmed delay value. The internal
propagation delay is specified in the Beamformer Output Tim-
ing Characteristics with the programmable delay set at 0.
The user-defined delay value is set by programming the 17
Least Significant Bits in Registers 00h to 07h for each of the
8 output channels, respectively. The 17 Least Significant Bits
in Delay Profile Registers 00h to 07h (00-07h[17:0]) are fur-
ther divided into Coarse Delay Adjustment bits and Fine Delay
Adjustment bits.
Coarse Delay Adjustment
Bits 3 to 16 (00-07h[16:3]) set the internal programmable
counter, which in turn set the coarse delay value. These 14
bits control the number of internal clock cycles (ranging from
0 to 16,383) that the P/N output is delayed in addition to the
internal propagation delay.
Fine Delay Adjustment
Bits 0 to 2 (00-07h[2:0]) set the clock phase for the internal
programmable counter, which in turn set the fine delay value.
In addition to the coarse delay, these 3 bits control the frac-
tional amount of delay that the P/N output is delayed by
relative to the internal Fire signal. The fine delay is phase ad-
justable in increments of 1/8 of an internal clock cycle, i.e.,
45°. See Figure 5.
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LM96570