Datasheet

LM96163
www.ti.com SNAS433D –JUNE 2008–REVISED MAY 2013
Configuration Register
Address Read/ POR
Bits Name Description
Hex Write Value
03 (09)
HEX
CONFIGURATION REGISTER
ALERT Mask
0: ALERT interrupts are enabled.
7 0 ALTMSK
1: ALERT interrupts are masked, and the ALERT pin is always in a high
impedance (open) state.
Standby
0: the LM96163 is in operational mode, converting, comparing, and updating the
PWM output continuously.
1: the LM96163 enters a low power standby mode.
6 0 STBY
R/W In standby, continuous conversions are stopped, but a conversion/comparison
cycle may be initiated by writing any value to register 0x0F the One-shot Register.
Operation of the PWM output in standby depends on the setting of bit 5 in this
register.
PWM Disable in Standby
0: the LM96163’s PWM output continues to output the current fan control signal
5 0 PWMDIS while in STANDBY.
03 (09)
1: the PWM output is disabled (as defined by the PWM polarity bit) while in
STANDBY.
R 4:3 00 [Reserved] This bit is unused and always read as 0.
TACH Enable
2 0 TCHEN 0: disables the TACH input
1: enables the TACH input
T_CRIT Limit Override
1 0 TCRITOV 0: locks the T_CRIT limit for the remote diode, POR setting is nominally 110°C
1: unlocks the T_CRIT limit and allows it to be reprogrammed multiple times
R/W
RDTS Fault Queue
0: an ALERT will be generated if any Remote Diode conversion result is above the
Remote High Set Point or below the Remote Low Setpoint.
0 0 FLTQUE
1: an ALERT will be generated only if three consecutive Remote Diode
conversions are above the Remote High Set Point or below the Remote Low
Setpoint.
Tachometer Count and Limit Registers
Address Read/ POR
Bits Name Description
Hex Write Value
47
HEX
TACHOMETER COUNT (MSB) and 46
HEX
TACHOMETER COUNT (LSB) REGISTERS (16 bits: Read LSB first to lock MSB and
ensure MSB and LSB are from the same reading)
47 R 7:0 N/A TAC13:TAC6 Tachometer Count (MSB and LSB)
These registers contain the current 16-bit Tachometer Count, representing the
period of time between tach pulses.
R 7:2 N/A TAC5:TAC0
Note that the 16-bit tachometer MSB and LSB register addresses are in reverse
order from the 16 bit temperature readings.
Tachometer Edge Programming
Bits Edges Used Tach_Count_Multiple
46
00: Reserved - do not use
01: 2 4
R 1:0 00 TEDGE1:TEDGE0
10: 3 2
11: 5 1
Note: If PWM_Clock_Select = 360 kHz, then Tach_Count_Multiple = 1 regardless
of the setting of these bits.
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