Datasheet

LM96163
SNAS433D –JUNE 2008–REVISED MAY 2013 www.ti.com
LM96163 DETAILED REGISTER DESCRIPTIONS IN FUNCTIONAL ORDER
The following is a Register Map grouped in functional and sequence order. New register addresses have been
added to maintain compatibility with the LM63 and LM64 register sets. Addresses in parenthesis are mirrors of
named address for backwards compatibility with some older software. Reading or writing either address will
access the same 8-bit register.
Fan Control Registers
Address Read/ POR
Bits Name Description
Hex Write Value
45
HEX
ENHANCED CONFIGURATION
R 7 0 [Reserved] This bit is unused and always read as 0.
Signed Temperature Filter Bits Enable
0: external signed temperature LSbs [4:3] will always read "0" (backwards
R/W 6 0 STFBE compatible with the LM63)
1: when the digital filter is enabled the external signed temperature LSbs [4:3]
(1/16 and 1/32 resolution) are enabled
Lookup Table Resolution Extension
0: LUT temperature resolution 7-bits (LSb = 1°C, backwards compatible with the
R/W 5 0 LRES
LM63)
1: enable 8-bit LUT temperature resolution (LSb extended to 0.5°C)
22.5kHz PWM High Resolution Control (only effective when PWM frequency set to
22.5kHz)
R/W 4 0 PHR
0: PWM resolution 6.25% (backwards compatible with the LM63)
1: enable high resolution (0.39%)
Unsigned High and T_CRIT Setpoint Format
0: enable signed format for High and T_CRIT setpoints (11-bit is -128.000°C to
R/W 3 0 USF 127.875°C or 8-bit is -128°C to 127°C)
1: enable unsigned format for High and T_CRIT setpoints (11-bit is 0°C to
255.875°C or 8-bit is 0°C to 255°C)
45
PWM Smoothing Ramp Rate Setting (these bits can modified only when PWM
Programming is enabled, 0x4A[5]=1)
00: 0.023 s per step (5.45 seconds for 0 to 100% duty cycle transition with 0.39%
resolution)
01: 0.046 s per step (10.9 seconds for 0 to 100% duty cycle transition with 0.39%
resolution)
R/W 2:1 00 RRS1:RRS0 10: 0.91 s per step (21.6 seconds for 0 to 100% duty cycle transition with 0.39%
resolution)
11: 0.182 s per step (43.7 seconds for 0 to 100% duty cycle transition with 0.39%
resolution)
Note: PWM smoothing is disabled for PWM spinup and for duty cycle setting
override caused by a TCRIT event, thus it is only enabled during LUT transitions.
PWM smoothing is only effective when PWM frequency is set to 22.5kHz.
PWM Smoothing Ramp Rate Control (this bit can modified only when the PWM
Programming is enabled, 0x4A[5]=1)
0: PWM smoothing disabled (LM63 backwards compatible)
R/W 0 0 PSRR 1: enable ramp rate control (as controlled by 0x45[2:1])
Note: PWM smoothing is disabled for PWM spinup and for duty cycle setting
override caused by a TCRIT event, thus it is only enabled during LUT transitions.
PWM smoothing is only effective when PWM frequency is set to 22.5kHz
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