Datasheet

LM96080
SNAS465D –SEPTEMBER 2009–REVISED MARCH 2013 www.ti.com
When using the Serial Bus Interface, a write will always consists of the LM96080 Serial Bus Interface Address
byte, followed by the Internal Address Register byte, then the data byte.
There are two cases for a read:
1. If the Internal Address Register is known to be at the desired Address, simply read the LM96080 with the
Serial Bus Interface Address byte, followed by the data byte read from the LM96080.
2. If the Internal Address Register value is unknown, write to the LM96080 with the Serial Bus Interface
Address byte, followed by the Internal Address Register byte. Then restart the Serial Communication with a
Read consisting of the Serial Bus Interface Address byte, followed by the data byte read from the LM96080.
The default power on Serial Bus address for the LM96080 is 0101(A2)(A1)(A0) binary, where A0-A2 are the
Serial Bus Address.
All of the combinations of communications supported by the LM96080 are depicted in the Serial Bus Interface
Timing Diagrams as shown in Figure 13.
USING THE LM96080
Power On
When power is first applied, the LM96080 performs a “power on reset” on several of its registers. The power on
condition of registers is shown in Table 1. Registers whose power on values are not shown have power on
conditions that are indeterminate (this includes the value RAM and WATCHDOG limits). In most applications,
usually the first action after power-on would be to write WATCHDOG limits into the Value RAM.
Resets
Configuration Register INITIALIZATION bit (address 00h, bit 7) accomplishes the same function as power on
reset. The Value RAM conversion results (addresses 20h - 29h) and Value RAM WATCHDOG limits (addresses
2Ah - 3Dh) are not reset and will be indeterminate immediately after power on. If the Value RAM contains valid
conversion results and/or Value RAM WATCHDOG limits have been previously set, they will not be affected by
the Configuration Register INITIALIZATION (except for addresses 3Eh and 3Fh). Power on reset or
Configuration Register INITIALIZATION bit clear or initialize the following registers (the initialized values are
shown in Table 1):
1. Configuration Register
2. Interrupt Status Register 1
3. Interrupt Status Register 2
4. Interrupt Mask Register 1
5. Interrupt Mask Register 2
6. Fan Divisor/RST_OUT/OS Register
7. OS Configuration/Temperature Resolution Register
8. Conversion Rate Register
9. Voltage/Temperature Channel Disable Register
10. Value RAM Registers (only addresses 3Eh and 3Fh)
Configuration Register INITIALIZATION is accomplished by setting bit 7 of the Configuration Register (address
00h) high. This bit automatically clears after being set.
The LM96080 can be reset to its “power on state” by taking NTEST_IN/Reset_IN pin low for at least 50 ns.
The time it takes for NTEST_IN/Reset_IN rising edge to SDA falling edge is at least t
RSDA
, and for
NTEST_IN/Reset_IN rising edge to SCL falling edge is at least t
RSCL
. Refer to the AC Electrical Characteristics
for more information on t
RSDA
and t
RSCL
.
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