Datasheet

SNP
GND
D1
PIN
V
IH
V
IL
SMBCLK
P
S
V
IH
V
IL
SMBDAT
t
BUF
t
HD;STA
t
LOW
t
R
t
HD;DAT
t
HIGH
t
F
t
SU;DAT
t
SU;STA
t
SU;STO
PS
LM96000
www.ti.com SNAS234C –APRIL 2004–REVISED MARCH 2013
AC Electrical Characteristics (continued)
The following specifications apply for V+ = 3.0V to 3.6V unless otherwise specified in conditions. Boldface limits apply for
T
A
= T
J
over T
MIN
=0°C to T
MAX
=85°C; all other limits T
A
=T
J
= 25°C.
Typical Limits Units
Parameter Test Conditions
(1) (2)
(Limits)
SMBUS TIMING CHARACTERISTICS
f
SMB
SMBus Operating Frequency 10 kHz (min)
100 kHz (max)
f
BUF
SMBus Free Time Between Stop And 4.7 µs (min)
Start Condition
t
HD_STA
Hold Time After (Repeated) Start 4.0 µs (min)
Condition (after this period, the first clock
is generated)
t
SU:STA
Repeated Start Condition Setup Time 4.7 µs (min)
t
SU:STO
Stop Condition Setup Time 4.0 µs (min)
t
HD:DAT
Data Output Hold Time 300 ns (min)
930 ns (max)
t
SU:DAT
Data Input Setup Time 250 ns (min)
t
TIMEOUT
Data And Clock Low Time To Reset Of 25 ms (min)
SMBus Interface Logic
(3)
35 ms (max)
t
LOW
Clock Low Period 4.7 µs (min)
t
HIGH
Clock High Period 4.0 µs (min)
50 µs (max)
t
F
Clock/Data Fall Time 300 ns (max)
t
R
Clock/Data Rise Time 1000 ns (max)
t
POR
Time from Power-On-Reset to LM96000 V+ > 2.8V 500 ms (max)
Reset and Operational
(3) Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than t
TIMEOUT
will reset the LM96000's SMBus state machine,
therefore setting the SMBDAT pin to a high impedance state.
Pin Pin Name Circuit All Input Circuits
No.
1 SMBDAT A
2 SMBCLK
3 GND B
4 3.3V
Figure 2. Circuit A
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LM96000