Datasheet
V
IH
V
IL
SMBCLK
P
S
V
IH
V
IL
SMBDAT
t
BUF
t
HD;STA
t
LOW
t
R
t
HD;DAT
t
HIGH
t
F
t
SU;DAT
t
SU;STA
t
SU;STO
PS
LM95245
www.ti.com
SNIS148G –OCTOBER 2007–REVISED MARCH 2013
SMBus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for V
DD
= +3.0 Vdc to +3.6 Vdc, C
L
(load capacitance) on output lines = 80
pF. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25°C, unless otherwise noted.
The switching characteristics of the LM95245 fully meet or exceed the published specifications of the SMBus version 2.0. The
following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM95245. They
adhere to, but are not necessarily, the SMBus specifications.
Unit
Parameter Test Conditions Typ
(1)
Limits
(2)
(Limit)
100 kHz (max)
f
SMB
SMBus Clock Frequency
10 kHz (min)
4.7 µs (min)
t
LOW
SMBus Clock Low Time from V
IN(0)
max to V
IN(0)
max
25 ms (max)
t
HIGH
SMBus Clock High Time from V
IN(1)
min to V
IN(1)
min 4.0 µs (min)
t
R,SMB
SMBus Rise Time
(3)
1 µs (max)
t
F,SMB
SMBus Fall Time
(4)
0.3 µs (max)
C
L
= 400 pF,
t
OF
Output Fall Time 250 ns (max)
I
O
= 3 mA,
(4)
SMBDAT and SMBCLK Time Low for Reset of 25 ms (min)
t
TIMEOUT
Serial Interface
(5)
35 ms (max)
t
SU;DAT
Data In Setup Time to SMBCLK High 250 ns (min)
300 ns (min)
t
HD;DAT
Data Out Stable after SMBCLK Low
1075 ns (max)
Start Condition SMBDAT Low to SMBCLK Low
t
HD;STA
(Start condition hold before the first clock falling 100 ns (min)
edge)
Stop Condition SMBCLK High to SMBDAT Low
t
SU;STO
100 ns (min)
(Stop Condition Setup)
SMBus Repeated Start-Condition Setup Time,
t
SU;STA
0.6 µs (min)
SMBCLK High to SMBDAT Low
SMBus Free Time Between Stop and Start
t
BUF
1.3 µs (min)
Conditions
(1) Typical figures are at T
A
= 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not guaranteed.
(2) Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
(3) The output rise time is measured from (V
IN(0)
max - 0.15V) to (V
IN(1)
min + 0.15V).
(4) The output fall time is measured from (V
IN(1)
min + 0.15V) to (V
IN(0)
max - 0.15V).
(5) Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than t
TIMEOUT
will reset the LM95245's SMBus state machine,
therefore setting SMBDAT and SMBCLK pins to a high impedance state.
Figure 2. SMBus Communication
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