Datasheet
V
IH
V
IL
SMBCLK
P
S
V
IH
V
IL
SMBDAT
t
BUF
t
HD;STA
t
LOW
t
R
t
HD;DAT
t
HIGH
t
F
t
SU;DAT
t
SU;STA
t
SU;STO
PS
LM95235
LM95235-Q1
www.ti.com
SNIS142F –APRIL 2006–REVISED MARCH 2013
SMBus Digital Switching Characteristics (continued)
Unless otherwise noted, these specifications apply for V
DD
= +3.0 Vdc to +3.6 Vdc, C
L
(load capacitance) on output lines = 80
pF. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25°C, unless otherwise noted.
The switching characteristics of the LM95235 fully meet or exceed the published specifications of the SMBus version 2.0. The
following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM95235. They
adhere to, but are not necessarily, the SMBus specifications.
Parameter Test Conditions Typical Limits Unit
(1) (2)
(Limit)
C
L
= 400 pF,
t
OF
Output Fall Time 250 ns (max)
I
O
= 3 mA,
(4)
SMBDAT and SMBCLK Time Low for 25 ms (min)
t
TIMEOUT
Reset of Serial Interface
(5)
35 ms (max)
t
SU;DAT
Data In Setup Time to SMBCLK High 250 ns (min)
300 ns (min)
t
HD;DAT
Data Out Stable after SMBCLK Low
1075 ns (max)
Start Condition SMBDAT Low to
t
HD;STA
SMBCLK Low (Start condition hold 100 ns (min)
before the first clock falling edge)
Stop Condition SMBCLK High to
t
SU;STO
100 ns (min)
SMBDAT Low (Stop Condition Setup)
SMBus Repeated Start-Condition Setup
t
SU;STA
0.6 µs (min)
Time, SMBCLK High to SMBDAT Low
SMBus Free Time Between Stop and
t
BUF
1.3 µs (min)
Start Conditions
(5) Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than t
TIMEOUT
will reset the LM95235's SMBus state machine,
therefore setting SMBDAT and SMBCLK pins to a high impedance state.
Figure 2. SMBus Communication
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