Datasheet
LM95235
LM95235-Q1
SNIS142F –APRIL 2006–REVISED MARCH 2013
www.ti.com
Logic Electrical Characteristics
Digital DC Characteristics
Unless otherwise noted, these specifications apply for V
DD
= +3.0 Vdc to 3.6 Vdc. Boldface limits apply for T
A
= T
J
= T
MIN
to
T
MAX
; all other limits T
A
= T
J
= +25°C, unless otherwise noted.
Unit
Symbol Parameter Test Conditions Typical
(1)
Limits
(2)
(Limit)
SMBDAT, SMBCLK INPUTS
V
IN(1)
Logical “1” Input Voltage 2.1 V (min)
V
IN(0)
Logical “0” Input Voltage 0.8 V (max)
SMBDAT and SMBCLK Digital Input
V
IN(HYST)
400 mV
Hysteresis
I
IN(1)
Logical “1” Input Current V
IN
= V
DD
-0.005 -10 µA (max)
I
IN(0)
Logical “0” Input Current V
IN
= 0 V 0.005 +10 µA (max)
C
IN
Input Capacitance 5 pF
A0 DIGITAL INPUT
V
IH
Input High Voltage 0.90 × V
DD
V (min)
0.57 × V
DD
V (max)
V
IM
Input Middle Voltage
0.43 × V
DD
V (min)
V
IL
Input Low Voltage 0.10 × V
DD
V (max)
I
IN(1)
Logical “1” Input Current V
IN
= V
DD
-0.005 -10 µA (max)
I
IN(0)
Logical “0” Input Current V
IN
= 0 V 0.005 +10 µA (max)
C
IN
Input Capacitance 5 pF
SMBDAT, T_CRIT, OS DIGITAL OUTPUTS
I
OH
High Level Output Leakage Current V
OUT
= V
DD
10 µA (max)
V
OL(T_CRIT,
T_CRIT, OS Low Level Output Voltage I
OL
= 6 mA 0.4 V (max)
OS)
I
OL
= 4 mA 0.4 V (max)
V
OL(SMBDAT)
SMBDAT Low Level Output Voltage
I
OL
= 6 mA 0.6 V (max)
C
OUT
Digital Output Capacitance 5 pF
(1) Typical figures are at T
A
= 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not guaranteed.
(2) Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
SMBus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for V
DD
= +3.0 Vdc to +3.6 Vdc, C
L
(load capacitance) on output lines = 80
pF. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25°C, unless otherwise noted.
The switching characteristics of the LM95235 fully meet or exceed the published specifications of the SMBus version 2.0. The
following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM95235. They
adhere to, but are not necessarily, the SMBus specifications.
Parameter Test Conditions Typical Limits Unit
(1) (2)
(Limit)
100 kHz (max)
f
SMB
SMBus Clock Frequency
10 kHz (min)
4.7 µs (min)
t
LOW
SMBus Clock Low Time from V
IN(0)
max to V
IN(0)
max
25 ms (max)
t
HIGH
SMBus Clock High Time from V
IN(1)
min to V
IN(1)
min 4.0 µs (min)
t
R,SMB
SMBus Rise Time
(3)
1 µs (max)
t
F,SMB
SMBus Fall Time
(4)
0.3 µs (max)
(1) Typical figures are at T
A
= 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not guaranteed.
(2) Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
(3) The output rise time is measured from (V
IN(0)
max - 0.15V) to (V
IN(1)
min + 0.15V).
(4) The output fall time is measured from (V
IN(1)
min + 0.15V) to (V
IN(0)
max - 0.15V).
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