Datasheet
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
LM95235
Start by
Master
Frame 1
Serial Bus Address Byte
Frame 2
Data Byte from the LM95235
NoAck
by
Master
SMBCLK
SMBDAT
Stop
by
Master
R/W
A5 A3 A2 A0A6 A4 A1
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
LM95235
Start by
Master
Frame 1
Serial Bus Address Byte
Frame 2
Command Byte
Ack
by
LM95235
D7 D6 D5 D4 D3 D2 D1 D0
1 9
Frame 3
Data Byte
Ack by
LM95235
Stop
by
Master
SMBCLK
SMBDAT
SMBCLK
(Continued)
SMBDAT
(Continued)
R/W
A5 A3 A2 A0A6 A4 A1
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
LM95235
Start by
Master
R/W
Frame 1
Serial Bus Address Byte
Frame 2
Command Byte
Ack by
LM95235
SMBCLK
SMBDAT
A5 A3 A2 A0A6 A4 A1
Stop
by
Master
LM95235
LM95235-Q1
SNIS142F –APRIL 2006–REVISED MARCH 2013
www.ti.com
The data byte has the most significant bit first. At the end of a read, the LM95235 can accept either acknowledge
or No Acknowledge from the Master (No Acknowledge is typically used as a signal for the slave that the Master
has read its last byte). When retrieving all 11 bits from a previous remote diode temperature measurement, the
master must insure that all 11 bits are from the same temperature conversion. This may be achieved by reading
the MSB register first. The LSB will be locked after the MSB is read. The LSB will be unlocked after being read. If
the user reads MSBs consecutively, each time the MSB is read, the LSB associated with that temperature will be
locked in and override the previous LSB value locked-in.
Figure 14. SMBus Timing Diagram for Access of Data (Default Address of 4Ch is shown)
(a) Serial Bus Write to the Internal Command Register
Figure 15. SMBus Timing Diagram for Access of Data (Default Address of 4Ch is shown)
(b) Serial Bus Write to the Internal Command Register Followed by a Data Byte
Figure 16. SMBus Timing Diagram for Access of Data (Default Address of 4Ch is shown)
(c) Serial Bus Byte Read from a Register with the Internal Command Register Preset to Desired Value
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Product Folder Links: LM95235 LM95235-Q1