Datasheet
SNP
GND
D1
PIN
GND
PIN
D1
V+
6.5V
D3
ESD
CLAMP
D2
V
IH
V
IL
SMBCLK
P
S
V
IH
V
IL
SMBDAT
t
BUF
t
HD;STA
t
LOW
t
R
t
HD;DAT
t
HIGH
t
F
t
SU;DAT
t
SU;STA
t
SU;STO
PS
LM95234
www.ti.com
SNIS136D –AUGUST 2006–REVISED MARCH 2013
SMBus DIGITAL SWITCHING CHARACTERISTICS (continued)
Unless otherwise noted, these specifications apply for V
DD
=+3.0 Vdc to +3.6 Vdc, C
L
(load capacitance) on output lines = 80
pF. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25°C, unless otherwise noted.
The switching characteristics of the LM95234 fully meet or exceed the published specifications of the SMBus version 2.0. The
following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM95234. They
adhere to but are not necessarily the SMBus bus specifications.
Symbol Parameter Conditions Typical
(1)
Limits
(2)
Units
(Limit)
t
TIMEOUT
SMBDAT and SMBCLK Time Low for Reset of 25 ms (min)
Serial Interface
(5)
35 ms (max)
t
SU;DAT
Data In Setup Time to SMBCLK High 250 ns (min)
t
HD;DAT
Data Out Stable after SMBCLK Low 300 ns (min)
1075 ns (max)
t
HD;STA
Start Condition SMBDAT Low to SMBCLK Low 100 ns (min)
(Start condition hold before the first clock falling
edge)
t
SU;STO
Stop Condition SMBCLK High to SMBDAT Low 100 ns (min)
(Stop Condition Setup)
t
SU;STA
SMBus Repeated Start-Condition Setup Time, 0.6 µs (min)
SMBCLK High to SMBDAT Low
t
BUF
SMBus Free Time Between Stop and Start 1.3 µs (min)
Conditions
(5) Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than t
TIMEOUT
will reset the LM95234's SMBus state machine,
therefore setting SMBDAT and SMBCLK pins to a high impedance state.
Figure 2. SMBus Communication
Table 1. Parasitic components and ESD protection circuitry
Pin # Label Circuit Circuits for Pin ESD Protection Structure
1 NC –
2 V
DD
A
3 D4+ A
4 D3+ A
5 D- A
6 D2+ A
7 D1+ A Circuit A
8 GND –
9 A0 B
10 TCRIT1 B
11 TCRIT2 B
12 SMBDAT B
13 SMBCLK B
14 TCRIT2 B Circuit B
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