Datasheet

D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
LM95233
Start by
Master
Repeat
Start by
Master
R/W
Frame 1
Serial Bus Address Byte
Frame 2
Command Byte
Ack
by
LM95233
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
LM95233
R/W
Frame 3
Serial Bus Address Byte
Frame 4
Data Byte from the LM95233
No Ack
by
Master
Stop
by
Master
SMBCLK
SMBDAT
SMBCLK
(Continued)
SMBDAT
(Continued)
A5 A3 A2 A0A6 A4 A1
A5 A3 A2 A0A6 A4 A1
D7 D6 D5 D4 D3 D2 D1 D0
1 9 1 9
Ack
by
LM95233
Start by
Master
R/W
Frame 1
Serial Bus Address Byte
Frame 2
Data Byte from the LM95233
NoAck
by
Master
SMBCLK
SMBDAT
Stop
by
Master
A5 A3 A2 A0
A6 A4
A1
LM95233
SNIS145E –AUGUST 2006–REVISED MARCH 2013 www.ti.com
Figure 18. (c) Serial Bus Read from a Register with the Internal Command Register preset to desired
value.
Figure 19. (d) Serial Bus Write followed by a Repeat Start and Immediate Read
SERIAL INTERFACE RESET
In the event that the SMBus Master is RESET while the LM95233 is transmitting on the SMBDAT line, the
LM95233 must be returned to a known state in the communication protocol. This may be done in one of two
ways:
1. When SMBDAT is LOW, the LM95233 SMBus state machine resets to the SMBus idle state if either
SMBDAT or SMBCLK are held low for more than 35ms (t
TIMEOUT
). Note that according to SMBus
specification 2.0 all devices are to timeout when either the SMBCLK or SMBDAT lines are held low for 25-
35ms. Therefore, to insure a timeout of all devices on the bus the SMBCLK or SMBDAT lines must be held
low for at least 35ms.
2. When SMBDAT is HIGH, have the master initiate an SMBus start. The LM95233 will respond properly to an
SMBus start condition at any point during the communication. After the start the LM95233 will expect an
SMBus Address address byte.
ONE-SHOT CONVERSION
The One-Shot register is used to initiate a round of conversions and comparisons when the device is in standby
mode, after which the device returns to standby. This is not a data register and it is the write operation that
causes the one-shot conversion. The data written to this address is irrelevant and is not stored. A zero will
always be read from this register. All the channels that are enabled in the Channel Enable Register will be
converted once and the TCRIT1, TCRIT2 and TCRIT3 pins will reflect the comparison results based on this
round of conversion results of the channels that are not masked.
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