Datasheet

LM95231
www.ti.com SNIS139E –FEBRUARY 2005–REVISED MARCH 2013
2. When SMBDAT is HIGH, have the master initiate an SMBus start. The LM95231 will respond properly to an
SMBus start condition at any point during the communication. After the start the LM95231 will expect an
SMBus Address address byte.
ONE-SHOT CONVERSION
The One-Shot register is used to initiate a single conversion and comparison cycle when the device is in standby
mode, after which the device returns to standby. This is not a data register and it is the write operation that
causes the one-shot conversion. The data written to this address is irrelevant and is not stored. A zero will
always be read from this register.
LM95231 Registers
Command register selects which registers will be read from or written to. Data for this register should be
transmitted during the Command Byte of the SMBus write communication.
P7 P6 P5 P4 P3 P2 P1 P0
Command
P0-P7: Command
Table 6. Register Summary
Name Command Power-On Read/Write # of used bits Comments
(Hex) Default Value
(Hex)
Status Register 02h - RO 5 4 status bits and 1 busy bit
Configuration Register 03h 00h R/W 5 Includes conversion rate control
Remote Diode Filter Control 06h 05h R/W 2 Controls thermal diode filter
setting
Remote Diode Model Type 30h 01h R/W 2 Selects the 2N3904 or Pentium
Select 4 processor on 90nm process
thermal diode model
Remote Diode TruTherm Mode 07h 01h 8 Enables or disables TruTherm
Control technology for Remote Diode
measurements
1-shot 0Fh - WO - Activates one conversion for all
3 channels if the chip is in
standby mode (i.e. RUN/STOP
bit = 1). Data transmitted by the
host is ignored by the LM95231.
Local Temperature MSB 10h - RO 8
Remote Temperature 1 MSB 11h - RO 8
Remote Temperature 2 MSB 12h - RO 8
Local Temperature LSB 20h - RO 2 All unused bits will report zero
Remote Temperature 1 LSB 21h - RO 3/5 All unused bits will report zero
Remote Temperature 2 LSB 22h - RO 3/5 All unused bits will report zero
Manufacturer ID FEh 01h RO
Revision ID FFh A1h RO
STATUS REGISTER
D7 D6 D5 D4 D3 D2 D1 D0
Busy Reserved R2TME R1TME RD2M RD1M
0 0 0
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