Datasheet
Table Of Contents
- FEATURES
- Applications
- Key Specifications
- DESCRIPTION
- Absolute Maximum Ratings
- Operating Ratings
- Package Thermal Resistances
- Temperature-to-Digital Converter Characteristics
- Logic Electrical Characteristics Digital DC Characteristics
- Serial Bus Digital Switching Characteristics
- Functional Description
- Revision History

Temperature Reg Read
(16 bits)
CS
SI/O
D16 D0
SC
1 16
Measured
Temperature
T
HIGH
Limit
T
LOW
Limit
OVERTEMP Reset
%LWVHWWR³1´
OVERTEMP Output
Polarity = Active Low
NOTE: The OVERTEMP output asserts when the measured temperature is greater than the T
HIGH
value.
Up to 1 Conversion Time
1 Conversion Time
LM95172
SNOSB33B –DECEMBER 2009–REVISED MARCH 2013
www.ti.com
Figure 10. LM95172EWG OVERTEMP vs. Temperature Response Diagram
The OVERTEMP Output will assert when the measured temperature is greater than the T
HIGH
value.
OVERTEMP will reset if any of the following events happen:
1. The temperature falls below the value stored in the T
LOW
register, or
2. A "1" is written to the OVERTEMP Reset bit in the Control/Status Register.
If OVERTEMP is cleared by the master writing a "1" to the OVERTEMP Reset bit while the measured
temperature still exceeds the T
HIGH
value, OVERTEMP will assert again after the completion of the next
temperature conversion. Placing the LM95172EWG in shutdown mode or triggering a one-shot conversion does
not cause OVERTEMP to reset.
COMMUNICATING WITH THE LM95172EWG
The serial interface consists of three lines: CS (Chip Select), SC (Serial Clock), and the bi-directional SI/O (Serial
I/O) data line. A high-to-low transition of the CS line initiates the communication. The master (processor) always
drives the chip select and the clock. The first 16 clocks shift the temperature data out of the LM95172EWG on
the SI/O line (a temperature read). Raising the CS at anytime during the communication will terminate this read
operation. Following this temperature read, the SI/O line becomes an input and a command byte can be written
to the LM95172EWG. This command byte contains a R/W bit and the address of the register to be
communicated with next (see INTERNAL REGISTER STRUCTURE). When writing, the data is latched in after
every 8 bits. The processor must write at least 8 bits in order to latch the data. If CS is raised before the falling
edge of the 8th command bit, no data will be latched into the command byte. If CS is raised after the 8th bit, but
before the 16th bit, of a write to a 16-bit data register, only the most significant byte of the data will be latched.
This command-data-command-data sequence may be performed as many times as desired.
Figure 11. Reading the Temperature Register
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