Datasheet

CS
SC
SO
CS
SC
SO
t
5
t
5
CS
SC
SO
t
3
t
2
t
4
t
1
t
4
t
r
t
f
LM95071, LM95071-Q1
SNIS137D –AUGUST 2004–REVISED SEPTEMBER 2013 www.ti.com
SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS
Unless otherwise noted, these specifications apply for V
DD
= 2.4V to 5.5V
(1)
; C
L
(load capacitance) on output lines = 100 pF
unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25°C, unless
otherwise noted.
Test Unit
Symbol Parameter Typical
(2)
Limits
(3)
Conditions (Limit)
t
1
SC (Clock) Period 0.16 µs (min)
DC (max)
t
2
CS Low to SC (Clock) High Set-Up Time 100 ns (min)
t
3
CS Low to Data Out (SO) Delay 70 ns (max)
t
4
SC (Clock) Low to Data Out (SO) Delay 70 ns (max)
t
5
CS High to Data Out (SO) TRI-STATE 200 ns (max)
t
6
SC (Clock) High to Data In (SI) Hold Time 50 ns (min)
t
7
Data In (SI) Set-Up Time to SC (Clock) High 30 ns (min)
t
8
SC (Clock) High to CS High Hold Time 50 ns (min)
(1) The LM95071/LM95071-Q1 will operate properly over the V
DD
supply voltage range of 2.4V to 5.5V.
(2) Typicals are at T
A
= 25°C and represent most likely parametric norm.
(3) Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
Figure 2. Data Output Timing Diagram
Figure 3. TRI-STATE Data Output Timing Diagram
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