Datasheet

LM92

SNIS110D –MARCH 2000–REVISED MARCH 2013

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INTERNAL REGISTER STRUCTURE

Figure 8.

There are four data registers in the LM92, selected by the Pointer register. At power-up the Pointer is set to “00”;

the location for the Temperature Register. The Pointer register latches the last location it was set to. In Interrupt

Mode, a read from the LM92 resets the INT output. Placing the device in Shutdown mode resets the INT and

T_CRIT_A outputs. All registers are read and write, except the Temperature register which is read only.

A write to the LM92 will always include the address byte and the Pointer byte. A write to the Configuration

LOW

, T

HIGH

, and T_CRIT registers require two data bytes.

Reading the LM92 can take place either of two ways: If the location latched in the Pointer is correct (most of the

time it is expected that the Pointer will point to the Temperature register because it will be the data most

frequently read from the LM92), then the read can simply consist of an address byte, followed by retrieving the

corresponding number of data bytes. If the Pointer needs to be set, then an address byte, pointer byte, repeat

start, and another address byte plus required number of data bytes will accomplish a read.

The first data byte is the most significant byte with most significant bit first, permitting only as much data as

necessary to be read to determine the temperature condition. For instance, if the first four bits of the temperature

data indicates a critical condition, the host processor could immediately take action to remedy the excessive

temperature. At the end of a read, the LM92 can accept either Acknowledge or No Acknowledge from the Master

(No Acknowledge is typically used as a signal for the slave that the Master has read its last byte).

An inadvertent 8-bit read from a 16-bit register, with the D7 bit low, can cause the LM92 to stop in a state where

the SDA line is held low as shown in Figure 9. This can prevent any further bus communication until at least 9

additional clock cycles have occurred. Alternatively, the master can issue clock cycles until SDA goes high, at

which time issuing a “Stop” condition will reset the LM92.

Product Folder Links: LM92