Datasheet

LM87
www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013
Figure 14. LM87 Interrupt Structure
RESET# I/O
RESET# is intended to provide a master reset to devices connected to this line. Setting Bit 4 in Configuration
Register 1 high outputs a 20 ms (minimum) low pulse on this line, at the end of which Bit 4 in the Configuration
Register automatically clears. Again, the label for this pin is only its suggested use. In applications where the
RESET# capability is not needed it can be used for any type of digital control that requires a 20 ms (mimimum)
active low, open-drain output.
RESET# operates as an input when not activated by Configuration Register 1. Setting this line low will reset all of
the registers in the LM87 to their power on default state. All Value RAM locations will not be affected except for
the DAC Data Register.
NAND TREE TESTS
A NAND tree is provided in the LM87 for Automated Test Equipment (ATE) board level connectivity testing.
DACOut/NTEST_IN, INT#, THERM#, V
+
and GND pins are excluded from NAND tree testing. Taking
DACOut/NTEST_IN high during power up activates the NAND Tree test mode. After the first SMBus access to
the LM87 the NAND Tree test mode is terminated and cannot be reactivated without repeating the power up
sequence. To perform a NAND tree test, all pins included in the NAND tree should be driven to 1 forcing the
ADD/NTEST_OUT high. Each individual pin starting with SMBData and concluding with RESET# (excluding
DACOut/NTEST_IN, INT#, THERM#, V
+
and GND) can be taken low with the resulting toggle observed on the
ADD/NTEST_OUT pin. Allow for a typical propagation delay of 500 ns.
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