Datasheet

LM87
www.ti.com SNAS034J –APRIL 2000–REVISED MARCH 2013
The third group of signals that will generate INT# outputs are Hardware Temperature errors, caused by
temperatures exceeding the hardware limits stored at 13h, 14h, 17h, and 18h.The internal temperature value is
compared with the Internal Temperature Hardware High Limits in Registers 13h and 17h. The external
temperature values are compared with the External Temperature Hardware High Limits in Registers 14h and
18h. The limits in Register 14h and 18h apply equally to the values of both D1 and D2. Both temperature values
are individually compared with both limit values.
The only difference between the different Hardware Limit registers is that by writing a 1 into Bit 1 of register 4Ah,
the contents of register 13h will be locked and cannot be reprogrammed. Similarly, the contents of register 14h
will be locked by writing a 1 into Bit 2 of register 4Ah. The registers can only be reprogrammed if Bit 7 of
Configuration Register 1 (40h) is written to re-Initialize the chip, or power is removed and reapplied. This feature
is provided to prevent software from unintentionally overwriting these important limits.
Again, we will assume that the temperature initially is below the Hardware Temperature setpoints. If the
temperature on a subsequent conversion is above any of the values stored in the Hardware Temperature Limit
registers, the INT# output will be asserted. Errors caused by exceeding these limits cannot be cleared by reading
the Interrupt Status Registers, and the INT# condition can only be cleared by clearing the Thermal INT# Enable
bit, by setting the INT#_Clear bit or by disabling INT# by clearing the INT#_Enable bit.
The final INT# source to consider is the THERM# input/output. THERM# can be pulled low by an external source
to generate an INT# output. Pulling THERM# low with external circuitry sets the corresponding THERM#
Interrupt Status Bit. If this bit is not masked, it will cause INT# to be asserted. Reading the Interrupt Status
Registers will clear the status bit and will cause INT# to be deasserted. If the external signal continues to pull
THERM# low, the Interrupt Status Bit will be reset at the completion of the next conversion cycle. This will again
assert the INT# output. Note that if the external circuitry pulls THERM# low, but this pin is already low due to the
THERM# output being active, this external signal cannot be sensed, and the THERM# Interrupt Status Bit will not
be set.
Interrupt Status Registers: Reading a Status Register will return the contents of the Register, and reset the
Register. A subsequent read done before the analog “round-robin” monitoring loop is complete will indicate a
cleared Register. Allow at least 600 ms to allow all Registers to be updated between reads. In summary, the
Interrupt Status Register clears upon being read, and requires at least 300 ms to be updated. When the Interrupt
Status Register clears, the hardware interrupt line will also clear until the Registers are updated by the monitoring
loop.
Interrupt Status Mirror Registers: The Interrupt Status Mirror Registers provide the same information that the
Interrupt Status Registers do. Reading the Status Mirror Registers, however, does not reset the status bits.
Interrupt Mask Registers: All sources which are combined to form the INT# output can be individually masked
via the two Interrupt Mask Registers at 43h, and 44h. The bits in the mask registers correspond directly to the
bits in the Interrupt Status Registers. Setting an Interrupt Mask bit inhibits that Interrupt Status Bit from
generating an INT# interrupt. Clearing a mask bit allows the corresponding status bit, if set, to generate INT#
outputs. Interrupt Status Bits will be set and cleared regardless of the state of corresponding Interrupt Mask Bits,
the mask bits merely allow or prevent the status bits from contributing to the generation of INT# outputs.
Enabling and Clearing INT#: The hardware Interrupt line (INT#) is enabled by setting the INT#_Enable bit at Bit
1 of Configuration Register 1. The INT# output can be cleared by setting the INT#_Clear bit which is Bit 3 of
Configuration Register 1. When this bit is high, the LM87 monitoring loop will stop. It will resume when the bit is
low.
Thermal Interrupt Mask: In some applications, the user may want to prevent all thermal error conditions from
causing INT# interrupts. The Thermal INT# Mask bit (Bit 0 of Configuration Register 2) is provided for this
purpose. The THERM# output discussed later is not affected by the status of the Thermal INT# Mask bit and will
function normally in response to temperature error conditions. If the Thermal INT# Mask bit is set, the interrupt
status for internal and external temperature, the THERM# input, and the hardware temperature error
comparisons, will continue to be updated every conversion cycle, but will not have any effect on the INT# output.
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