Datasheet

LM87

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SNAS034J –APRIL 2000–REVISED MARCH 2013

Bit 2 of Configuration Register 1 enables the THERM# Interrupt output when this bit is taken high.

Bit 3 of Configuration Register 1 clears the INT# output when set high, without affecting the contents of the

Interrupt Status Registers. The LM87 will stop monitoring. It will resume upon clearing of this bit.

Bit 4 of Configuration Register 1 provides an active low 20 ms (minimum) pulse at the RESET# output when set

high.

Bit 6 of Configuration Register 1 clears the THERM# output when set high, without affecting the contents of the

Interrupt Status Registers.

Bit 7 of Configuration Register 1 (the INITIALIZATION bit) resets the internal registers of the LM87 as described

in Resets.

Bit 7 of the CI_Clear Register provides an active low 20 ms (minimum) pulse at the CI# output pin when set high.

This is intended for resetting the Chassis Intrusion circuitry.

Bit 0 of Configuration Register 2 enables the INT# Interrupt output for THERM# events when set low. When this

bit is set high, THERM# error events will not affect the INT# output.

Bit 1 of Configuration Register 2 locks the value set in the Internal Temperature high limit register at 13h. The

value cannot be changed until a Power On Reset is performed.

Bit 2 of Configuration Register 2 locks the value set in the External Temperature high limit register at 14h. The

value cannot be changed until a Power On Reset is performed.

Bit 3 of Configuration Register 2 sets the THERM# output mode. When set to 0, the THERM# output functions in

default mode, when set to 1, THERM# operates in ACPI mode.

Bit 6 of Configuration Register 2, when set to 1, enables pin 21 as an active high (IRQ3) interrupt input. When

set to 0, this input is disabled as an IRQ interrupt.

Bit 7 of Configuration Register 2, when set to 1, enables pin 20 as an active high (IRQ4) interrupt input. When

set to 0, this input is disabled as an IRQ interrupt.

Bit 0 of the Channel Mode Register, when set to 1, configures pin 5 as AIN1. When set to 0, pin 5 is configured

as the FAN1 input.

Bit 1 of the Channel Mode Register, when set to 1, configures pin 6 as AIN2. When set to 0, pin 6 is configured

as the FAN2 input.

Bit 2 of the Channel Mode Register, when set to 0, configures pins 18 and 19 as +2.5V and V

CCP2

voltage inputs.

When set to 1, pins 18 and 19 are configured as a second remote temperature sensing channel.

Bit 3 of the Channel Mode Register, when set to 0, sets the nominal voltage for internal V

measurement to

3.3V. When set to 1, the nominal V

range is 5V.

Bit 4 of the Channel Mode Register, when set to 1, enables pin 24 as an active low (IRQ0) interrupt input. When

set to 0, this input is disabled as an IRQ interrupt.

Bit 5 of the Channel Mode Register, when set to 1, enables pin 23 as an active low (IRQ1) interrupt input. When

set to 0, this input is disabled as an IRQ interrupt.

Bit 6 of the Channel Mode Register, when set to 1, enables pin 22 as an active low (IRQ2) interrupt input. When

set to 0, this input is disabled as an IRQ interrupt.

Bit 7 of the Channel Mode Register, when set to 1, configures pins 20 to 24 as interrupt inputs. When set to 0,

pins 20 to 24 are configured as processor voltage ID pins.

Product Folder Links: LM87