Datasheet

LM87
SNAS034J –APRIL 2000–REVISED MARCH 2013 www.ti.com
All of these communications are depicted in the Serial Bus Interface Timing Diagrams as shown in Figure 8. The
example shown corresponds to the ADD pin tied to Vcc, so XY=01 and the resulting LM87 address is 0101101.
Serial Bus Timeout can be initiated by holding the SMBCLK line low for greater than t
TIMEOUT
(35 ms max). Serial
Bus Timeout resets the serial bus interface circuitry to the idle state and readies the LM87 for a new serial bus
communication.
USING THE LM87
Power On
When power is first applied, the LM87 performs a “power on reset” on several of its registers. The power on
condition of the LM87's registers is shown in Table 1 Registers whose power on values are not shown have
power on conditions that are indeterminate (this includes the value RAM ,exclusive of the DAC data, and
WATCHDOG limits). When power is first applied the ADC is inactive. In most applications, the first action after
power on is to write WATCHDOG limits into the Value RAM.
Resets
All register values, except the Programmed DAC Output can be returned to their "power on" default values by
taking the RESET# input low for at least TBD ns or by performing a Configuration Register INITIALIZATION. The
Value RAM conversion results, and Value RAM WATCHDOG limits are not Reset and will be indeterminate
immediately after power on. If the Value RAM contains valid conversion results and/or Value RAM WATCHDOG
limits have been previously set, they will not be affected by a Configuration Register INITIALIZATION. The Power
On Reset, RESET# input, and Configuration Register INITIALIZATION, clear or initialize the following registers
(the initialized values are shown on Table I). Power On Reset also sets the Programmed DAC Output to full
scale (FFh) Hardware High Limit registers 13h, and 14h will only be returned to default values if the "Write Once"
bits in Configuration Register 2 have not been set:
• Configuration Registers 1 and 2
• Channel Mode Register
• Hardware High Limit Registers
• Interrupt Status Register 1
• Interrupt Status Register 2
• Interrupt Status Mirror Register 1
• Interrupt Status Mirror Register 2
• Interrupt Mask Register 1
• Interrupt Mask Register 2
• Chassis Intrusion Clear Register
• VID/Fan Divisor Register
• VID4 Register
• Extended Mode Register
Configuration Register INITIALIZATION is accomplished by setting Bit 7 of Configuration Register 1 high. This bit
automatically clears after being set.
Configuration Registers and Channel Mode Register
The Configuration Registers and Channel Mode Register control the LM87 operation. At power on, the ADC is
stopped and INT_Clear is asserted, clearing the INT# hardwire output. These registers start and stop the LM87,
enable and disable interrupt output, configure the operation of dual function inputs, and provide the Reset
functions described in Resets.
Bit 0 of Configuration Register 1 controls the monitoring loop of the LM87. Setting Bit 0 low stops the LM87
monitoring loop and puts the LM87 in shutdown mode, reducing power consumption. Serial Bus communication
can take place with any register in the LM87 although activity on the SMBData and SMBCLK lines will increase
shutdown current, up to as much as maximum rated supply current, while the activity takes place. Taking Bit 0
high starts the monitoring loop, described in more detail subsequently.
Bit 1 of Configuration Register 1 enables the INT# Interrupt output when this bit is taken high.
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