Datasheet

LM828
SNOS035D –MARCH 2010–REVISED MAY 2013 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)(2)
Supply Voltage (V+ to GND, or GND to OUT) 5.8V
V+ and OUT Continuous Output Current 50 mA
Output Short-Circuit Duration to GND
(3)
1 sec.
Continuous Power Dissipation (T
A
= 25°C)
(4)
240 mW
T
JMax
(4)
150°C
θ
JA
(4)
300°C/W
Operating Junction Temperature Range −40°C to 85°C
Storage Temperature Range −65°C to +150°C
Lead Temp. (Soldering, 10 seconds) 300°C
ESD Rating
(5)
2kV
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when
operating the device beyond its rated operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) OUT may be shorted to GND for one second without damage. However, shorting OUT to V+ may damage the device and should be
avoided. Also, for temperatures above 85°C, OUT must not be shorted to GND or V+, or the device may be damaged.
(4) The maximum allowable power dissipation is calculated by using P
DMax
= (T
JMax
− T
A
)/θ
JA
, where T
JMax
is the maximum junction
temperature, T
A
is the ambient temperature, and θ
JA
is the junction-to-ambient thermal resistance of the package.
(5) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Electrical Characteristics
Limits in standard typeface are for T
J
= 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: V+ = 5V, C
1
= C
2
= 10 μF.
(1)
Symbol Parameter Condition Min Typ Max Units
V+ Supply Voltage R
L
=10kΩ 1.8 5.5 V
I
Q
Supply Current No Load 40 75 µA
115
R
OUT
Output Resistance
(2)
I
L
= 5 mA 20 65 Ω
f
OSC
Oscillator Frequency
(3)
Internal 12 24 56 kHz
f
SW
Switching Frequency
(3)
Measured at CAP+ 6 12 28 kHz
P
EFF
Power Efficiency I
L
= 5 mA 97 %
V
OEFF
Voltage Conversion Efficiency No Load 95 99.96 %
(1) In the test circuit, capacitors C
1
and C
2
are 10 µF, 0.3Ω maximum ESR capacitors. Capacitors with higher ESR will increase output
resistance, reduce output voltage and efficiency.
(2) Specified output resistance includes internal switch resistance and capacitor ESR. See the details in the application information.
(3) The output switches operate at one half of the oscillator frequency, f
OSC
= 2f
SW
.
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